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path: root/target-arm/cpu.h
AgeCommit message (Expand)Author
2014-09-29target-arm: Add support for VIRQ and VFIQpull-target-arm-20140929Edgar E. Iglesias
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias
2014-09-29target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias
2014-09-29target-arm: Add HCR_EL2Edgar E. Iglesias
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell
2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell
2014-08-19target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias
2014-06-19target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini
2014-05-27target-arm: A64: Register VBAR_EL3pull-target-arm-20140527Edgar E. Iglesias
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias
2014-05-27target-arm: Add a feature flag for EL3Edgar E. Iglesias
2014-05-27target-arm: Add a feature flag for EL2Edgar E. Iglesias
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias
2014-05-27target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias
2014-05-27target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias
2014-05-27target-arm: Use a 1:1 mapping between EL and MMU indexEdgar E. Iglesias
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell
2014-04-17target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell
2014-04-17target-arm: Implement AArch64 SPSR_EL1Peter Maydell
2014-04-17target-arm: Implement SP_EL0, SP_EL1Peter Maydell
2014-04-17target-arm: Add AArch64 ELR_EL1 register.Peter Maydell
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring
2014-04-17target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell
2014-04-17target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell
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