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peter.maydell/qemu-arm.git
3phase-conversions
64-bit-physaddrs
a64-fifth-set
a64-first-set
a64-first-set-test-context
a64-for-marcus
a64-neon
a64-neon-sixth-set
a64-saverestore
a64-second-set
a64-sixth-set
a64-system
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a64-third-fourth-set
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aarch32-guest
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aarch64
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amba-virtio
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be-fixes
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configury.for-upstream
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cp15-barriers
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cpu-copy-method
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drop-kvm32
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fsr-in-faultinfo
full-tz-enable
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gdbstub
gic-as-device
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gicv3
gicv3-virt
gicv4
gpio-pwr
handle-gicv3-only
hvf-stuff
icount-debug
idreg-asserts
idreg-fixes
int-fast16-t
int-flag
ivshmem
javac-noodling
kvm-arm
kvm-arm-dev-addr-test
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kvm-arm-irqchange
kvm-arm-onereg
kvm-arm-onereg-vfp
kvm-arm-onereg-working
kvm-arm-v12
kvm-arm-v13
kvm-arm-v14
kvm-arm-v17
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kvm-work
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libusb-warning
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missing-idregs
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multi-ases-2
mve-drop-1
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neon-decodetree
ninjatool-barf
no-uname
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non-utf-fixes
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objcc-cross
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overo
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psci-messing
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qemu-char-warning
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ranchu
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ranchu-linaro-beta1
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s390-barriers
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singlestep-rename
softfloat-types
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sparc-buildfix
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sparc-pagealign
sphinx-conv-broken
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sphinx-conversions-v5
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tz-migration
uart-edk-investigation
use-esr-magic
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v7m-qomify
v8-tz
v8m
vexpress-clocks
vfp-decodetree
vgic
virt-for-uefi
vixl-1.12
vmid16
x86-rdtsc
xopen-source
This qemu repo is mostly a place to put together pull requests for upstream
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riscv
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Author
2022-01-08
hw/riscv: Use error_fatal for SoC realisation
Alistair Francis
2021-12-20
hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
Jessica Clarke
2021-12-15
hw: Replace trivial drive_get_next() by drive_get()
Markus Armbruster
2021-12-15
hw/sd/ssi-sd: Do not create SD card within controller's realize
Markus Armbruster
2021-10-28
hw/riscv: opentitan: Fixup the PLIC context addresses
Alistair Francis
2021-10-28
hw/riscv: virt: Use the PLIC config helper function
Alistair Francis
2021-10-28
hw/riscv: microchip_pfsoc: Use the PLIC config helper function
Alistair Francis
2021-10-28
hw/riscv: sifive_u: Use the PLIC config helper function
Alistair Francis
2021-10-28
hw/riscv: boot: Add a PLIC config string function
Alistair Francis
2021-10-28
hw/riscv: virt: Don't use a macro for the PLIC configuration
Alistair Francis
2021-10-22
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
2021-10-22
hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
2021-10-22
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
2021-10-22
hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
2021-10-22
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
2021-10-22
hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...
Bin Meng
2021-10-22
hw/riscv: opentitan: Update to the latest build
Alistair Francis
2021-10-22
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Richard Henderson
2021-10-22
hw/riscv: virt: Use machine->ram as the system memory
Mingwang Li
2021-10-07
hw/riscv: shakti_c: Mark as not user creatable
Alistair Francis
2021-09-21
hw/riscv: opentitan: Correct the USB Dev address
Alistair Francis
2021-09-21
hw/riscv: virt: Add optional ACLINT support to virt machine
Anup Patel
2021-09-21
hw/riscv: virt: Re-factor FDT generation
Anup Patel
2021-09-21
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
Anup Patel
2021-09-21
hw/intc: Rename sifive_clint sources to riscv_aclint sources
Anup Patel
2021-09-21
sifive_u: Connect the SiFive PWM device
Alistair Francis
2021-09-21
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Alistair Francis
2021-09-21
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Alistair Francis
2021-09-21
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Alistair Francis
2021-09-01
hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()
Peter Maydell
2021-09-01
hw/riscv: virt: Move flash node to root
Bin Meng
2021-09-01
hw/char: Add config for shakti uart
Vijai Kumar K
2021-08-26
arch_init.h: Don't include arch_init.h unnecessarily
Peter Maydell
2021-07-20
hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines
Philippe Mathieu-Daudé
2021-07-15
hw/riscv/boot: Check the error of fdt_pack()
Alistair Francis
2021-07-15
hw/riscv: opentitan: Add the flash alias
Alistair Francis
2021-07-15
hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Alistair Francis
2021-07-15
hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
Bin Meng
2021-07-15
hw/riscv: sifive_u: Correct the CLINT timebase frequency
Bin Meng
2021-06-24
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
Alistair Francis
2021-06-08
hw/riscv: microchip_pfsoc: Support direct kernel boot
Bin Meng
2021-06-08
hw/riscv: Use macros for BIOS image names
Bin Meng
2021-06-08
hw/riscv: Support the official PLIC DT bindings
Bin Meng
2021-06-08
hw/riscv: Support the official CLINT DT bindings
Bin Meng
2021-06-08
hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
Bin Meng
2021-06-08
hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
Bin Meng
2021-05-11
hw/riscv: Fix OT IBEX reset vector
Alexander Wagner
2021-05-11
hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Alistair Francis
2021-05-11
hw/opentitan: Update the interrupt layout
Alistair Francis
2021-05-11
hw/riscv: Connect Shakti UART to Shakti platform
Vijai Kumar K
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