path: root/hw/riscv
AgeCommit message (Expand)Author
2018-07-05hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis
2018-07-05hw/riscv/sifive_u: Move the uart device tree node under /soc/Alistair Francis
2018-07-05hw/riscv/sifive_u: Set the interrupt controller number of interruptsAlistair Francis
2018-07-05hw/riscv/sifive_u: Set the soc device tree node as a simple-busAlistair Francis
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis
2018-07-05hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis
2018-07-05hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis
2018-07-02hw/riscv: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé
2018-06-01hw: Do not include "exec/address-spaces.h" if it is not necessaryPhilippe Mathieu-Daudé
2018-05-10Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-...Peter Maydell
2018-05-09riscv: htif: increase the priority of the htif subregionKONRAD Frederic
2018-05-09riscv: spike: allow base == 0KONRAD Frederic
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark
2018-05-06RISC-V: Remove unused class definitionsMichael Clark
2018-05-06RISC-V: Remove identity_translate from load_elfMichael Clark
2018-05-06RISC-V: Use ROM base address and size from memmapMichael Clark
2018-05-06RISC-V: Make virt board description match spikeMichael Clark
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark
2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell
2018-03-07RISC-V Build InfrastructureMichael Clark
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark
2018-03-07SiFive RISC-V PRCI BlockMichael Clark
2018-03-07SiFive RISC-V UART DeviceMichael Clark
2018-03-07RISC-V VirtIO MachineMichael Clark
2018-03-07SiFive RISC-V Test FinisherMichael Clark
2018-03-07RISC-V Spike MachinesMichael Clark
2018-03-07SiFive RISC-V PLIC BlockMichael Clark
2018-03-07SiFive RISC-V CLINT BlockMichael Clark
2018-03-07RISC-V HART ArrayMichael Clark
2018-03-07RISC-V HTIF ConsoleMichael Clark