path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)Author
2018-07-05hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis
2018-07-05hw/riscv/sifive_u: Move the uart device tree node under /soc/Alistair Francis
2018-07-05hw/riscv/sifive_u: Set the interrupt controller number of interruptsAlistair Francis
2018-07-05hw/riscv/sifive_u: Set the soc device tree node as a simple-busAlistair Francis
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis
2018-07-05hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark
2018-05-06RISC-V: Remove unused class definitionsMichael Clark
2018-05-06RISC-V: Remove identity_translate from load_elfMichael Clark
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark
2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark