aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2014-05-13hw/net/stellaris_enet: Correct handling of packet paddingPeter Maydell
The PADEN bit in the transmit control register enables padding of short data packets out to the required minimum length. However a typo here meant we were adjusting tx_fifo_len rather than tx_frame_len, so the padding didn't actually happen. Fix this bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Cc: qemu-stable@nongnu.org
2014-05-13hw/net/stellaris_enet: Restructure tx_fifo code to avoid buffer overrunPeter Maydell
The current tx_fifo code has a corner case where the guest can overrun the fifo buffer: if automatic CRCs are disabled we allow the guest to write the CRC word even if there isn't actually space for it in the FIFO. The datasheet is unclear about exactly how the hardware deals with this situation; the most plausible answer seems to be that the CRC word is just lost. Implement this fix by separating the "can we stuff another word in the FIFO" logic from the "should we transmit the packet now" check. This also moves us closer to the real hardware, which has a number of ways it can be configured to trigger sending the packet, some of which we don't implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Cc: qemu-stable@nongnu.org
2014-05-13savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela
After commit 767adce2d, they are redundant. This way we don't assign them except when needed. Once there, there were lots of cases where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (apart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed minor conflict, corrected commit message typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-13disas/libvixl: Update to libvixl 1.4Peter Maydell
Update our copy of libvixl to upstream's 1.4 release. Note that we no longer need any local fixes for compilation on 32 bit hosts -- they have all been integrated upstream. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1399040419-9227-1-git-send-email-peter.maydell@linaro.org Acked-by: Richard Henderson <rth@twiddle.net>
2014-05-13Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20140512' into stagingPeter Maydell
tcg updates for 20140512 # gpg: Signature made Tue 13 May 2014 00:19:56 BST using RSA key ID 4DD0279B # gpg: Can't check signature: public key not found * remotes/rth/tags/pull-tcg-20140512: (26 commits) tcg: Remove unreachable code in tcg_out_op and op_defs tcg: Use tcg_target_available_regs in tcg_reg_alloc_mov tcg: Make call address a constant parameter tci: Create tcg_out_call tcg-mips: Split out tcg_out_call tcg-sparc: Create tcg_out_call tcg-ppc64: Rename tcg_out_calli to tcg_out_call tcg-ppc: Split out tcg_out_call tcg-s390: Rename tgen_calli to tcg_out_call tcg-i386: Rename tcg_out_calli to tcg_out_call tcg: Require TCG_TARGET_INSN_UNIT_SIZE tci: Define TCG_TARGET_INSN_UNIT_SIZE tcg-mips: Define TCG_TARGET_INSN_UNIT_SIZE tcg-ia64: Define TCG_TARGET_INSN_UNIT_SIZE tcg-s390: Define TCG_TARGET_INSN_UNIT_SIZE tcg-aarch64: Define TCG_TARGET_INSN_UNIT_SIZE tcg-arm: Define TCG_TARGET_INSN_UNIT_SIZE tcg-sparc: Define TCG_TARGET_INSN_UNIT_SIZE tcg-ppc: Define TCG_TARGET_INSN_UNIT_SIZE tcg-ppc64: Define TCG_TARGET_INSN_UNIT_SIZE ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-13bsd-user: Remove reference to CONFIG_UNAME_RELEASEPeter Maydell
Commit e586822a5 broke the bsd-user build when it removed the CONFIG_UNAME_RELEASE define but forgot to remove the use of it in bsd-user. Fix this in the simplest possible way (bsd-user doesn't make any use at all of the qemu_uname_release variable except to allow it to be pointlessly set by the user, so this is all we need to do.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1399648001-20980-1-git-send-email-peter.maydell@linaro.org
2014-05-13pc: port 92 reset requires a low->high transitionPaolo Bonzini
The PIIX datasheet says that "before another INIT pulse can be generated via [port 92h], [bit 0] must be written back to a zero. This bug is masked right now because a full reset will clear the value of port 92h. But once we implement soft reset correctly, the next attempt to enable the A20 line by setting bit 1 (and leaving the others untouched) will cause another reset. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini
On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13apic: do not accept SIPI on the bootstrap processorPaolo Bonzini
SIPI interrupts are ignored on the bootstrap. Never accept one. Cc: Andreas Faerber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: preserve FPU and MSR state on INITPaolo Bonzini
Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not be zeroed on INIT (Table 9-1 in the Intel SDM). Copy them out of CPUX86State and back in, instead of special casing env->pat. The relevant fields are already consecutive except PAT and SMBASE. However: - KVM and Hyper-V MSRs should be reset because they include memory locations written by the hypervisor. These MSRs are moved together at the end of the preserved area. - SVM state can be moved out of the way since it is written by VMRUN. Cc: Andreas Faerber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: fix set of registers zeroed on resetPaolo Bonzini
BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they should be (Intel Instruction Set Extensions Programming Reference 319433-015, pages 9-4 and 9-6). Same for YMM. XCR0 should be reset to 1. TSC and TSC_RESET were zeroed already by the memset, remove the explicit assignments. Cc: Andreas Faerber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13kvm: forward INIT signals coming from the chipsetPaolo Bonzini
Reviewed-by: Gleb Natapov <gnatapov@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13kvm: reset state from the CPU's reset methodPaolo Bonzini
Now that we have a CPU object with a reset method, it is better to keep the KVM reset close to the CPU reset. Using qemu_register_reset as we do now keeps them far apart. With this patch, PPC no longer calls the kvm_arch_ function, so it can get removed there. Other arches call it from their CPU reset handler, and the function gets an ARMCPU/X86CPU/S390CPU. Note that ARM- and s390-specific functions are called kvm_arm_* and kvm_s390_*, while x86-specific functions are called kvm_arch_*. That follows the convention used by the different architectures. Changing that is the topic of a separate patch. Reviewed-by: Gleb Natapov <gnatapov@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: the x86 CPL is stored in CS.selector - auto update hflags ↵Kevin O'Connor
accordingly. Instead of manually calling cpu_x86_set_cpl() when the CPL changes, check for CPL changes on calls to cpu_x86_load_seg_cache(R_CS). Every location that called cpu_x86_set_cpl() also called cpu_x86_load_seg_cache(R_CS), so cpu_x86_set_cpl() is no longer required. This fixes the SMM handler code as it was not setting/restoring the CPL level manually. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in ↵Kevin O'Connor
seg_helper.c The cpu_x86_load_seg_cache() function inspects eflags, so make sure all changes to eflags are done prior to loading the segment caches. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in ↵Kevin O'Connor
smm_helper.c The cpu_x86_load_seg_cache() function inspects cr0 and eflags, so make sure all changes to eflags and cr0 are done prior to loading the segment caches. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.cKevin O'Connor
The svm_load_seg_cache() function calls cpu_x86_load_seg_cache() which inspects env->eflags. So, make sure all changes to eflags are done prior to loading the segment cache. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13pci-assign: limit # of msix vectorsMichael S. Tsirkin
KVM only supports MSIX table size up to 256 vectors, but some assigned devices support more vectors, at the moment attempts to assign them fail with EINVAL. Tweak the MSIX capability exposed to guest to limit table size to a supported value. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Gonglei <arei.gonglei@huawei.com> Cc: qemu-stable@nongnu.org Acked-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13pci-assign: Fix a bug when map MSI-X table memory failedGonglei
When mmapping memory for the MSI-X table failsthe dev->msix_table is not set to NULL and assigned_dev_unregister_msix_mmio() will cause a segfault when trying to munmap it. Signed-off-by: Gonglei Arei <arei.gonglei@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Gonglei <arei.gonglei@huawei.com>
2014-05-13kvm: make one_reg helpers available for everyoneCornelia Huck
s390x introduced helper functions for getting/setting one_regs with commit 860643bc. However, nothing about these is s390-specific. Alexey Kardashevskiy had already posted a general version, so let's merge the two patches and massage the code a bit. CC: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13target-i386: Remove unused data from local arrayStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13Merge remote-tracking branch 'remotes/bonzini/configure' into stagingPeter Maydell
* remotes/bonzini/configure: libcacard: remove libcacard-specific CFLAGS and LIBS from global vars build: simplify and fix fix-obj-vars build: convert some obj-specific CFLAGS to use new foo.o-cflags syntax build: add support for per-object -cflags and -libs to all rules Makefile: use $(INSTALL_LIB) for modules not $(INSTALL_PROG) Makefile.target: use $(INSTALL_PROG) for installing, not $(INSTALL) Makefile: strip tools and modules too build: simplify Makefile.target around unnest-vars invocations build: simplify Makefile.target a bit, use just one rule for softmmu build: Fix per-object variables for Makefile.target Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-13Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Block pull request # gpg: Signature made Fri 09 May 2014 19:57:53 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/block-pull-request: glib: fix g_poll early timeout on windows block: qemu-iotests - test for live migration block: qemu-iotests - update 085 to use common.qemu block: qemu-iotests - add common.qemu, for bash-controlled qemu tests block/raw-posix: Try both FIEMAP and SEEK_HOLE gluster: Correctly propagate errors when volume isn't accessible vl.c: remove init_clocks call from main block: Fix open flags with BDRV_O_SNAPSHOT qemu-iotests: Test converting to streamOptimized from small cluster size vmdk: Implement .bdrv_get_info() vmdk: Implement .bdrv_write_compressed qemu-img: Convert by cluster size if target is compressed block/iscsi: bump year in copyright notice block/nfs: Check for NULL server part qemu-img: sort block formats in help message iotests: Use configured python qcow2: Fix alloc_clusters_noref() overflow detection Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-13microblaze: boot: Don't hack the elf entry pointPeter Crosthwaite
There was some modulo logic to ensure that Microblaze always booted into physical RAM regardless of the elf entry. Removed it, as QEMU should fail gracefully when given a bad elf, rather than attempt to run it. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-05-13xilinx_timer: Fix writes into TCSR registerGuenter Roeck
The TCSR register has only 11 valid bits. This is now used by the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1 and later to hang when run under qemu-microblaze. Mask valid bits before writing the register to solve the problem. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-05-13xilinx_intc: Fix writes into MER registerGuenter Roeck
The MER register only has two valid bits. This is now used by the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1 and later to hang when run under qemu-microblaze. Mask valid bits before writing the register to solve the problem. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> [Edgar: Untabified] Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-05-13microblaze: Respect the reset vectorEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-05-13microblaze: Support loading of u-boot initrd imagesEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-05-12target-i386: Preserve the Z bit for bt/bts/btr/btcRichard Henderson
Older Intel manuals (pre-2010) and current AMD manuals describe Z as undefined, but newer Intel manuals describe Z as unchanged. Cc: qemu-stable@nongnu.org Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Remove unreachable code in tcg_out_op and op_defsRichard Henderson
The INDEX_op_call case has just been obsoleted; the mov and movi cases have not been reachable for years. Attempt to document this both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT. Because of the TCG_OPF_NOT_PRESENT change, this must be done for all targets in a single commit. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Use tcg_target_available_regs in tcg_reg_alloc_movRichard Henderson
The move opcodes are special in that their constraints must cover all available registers. So instead of checking the constraints, just use the available registers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Make call address a constant parameterRichard Henderson
Avoid allocating a tcg temporary to hold the constant address, and instead place it directly into the op_call arguments. At the same time, convert to the newly introduced tcg_out_call backend function, rather than invoking tcg_out_op for the call. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tci: Create tcg_out_callRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-mips: Split out tcg_out_callRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-sparc: Create tcg_out_callRichard Henderson
Rename the existing tcg_out_calli to tcg_out_call_nodelay. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ppc64: Rename tcg_out_calli to tcg_out_callRichard Henderson
Merge the existing tcg_out_call into tcg_out_op. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ppc: Split out tcg_out_callRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-s390: Rename tgen_calli to tcg_out_callRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-i386: Rename tcg_out_calli to tcg_out_callRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Require TCG_TARGET_INSN_UNIT_SIZERichard Henderson
Now that all backends do define TCG_TARGET_INSN_UNIT_SIZE, remove the fallback definition. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tci: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-mips: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ia64: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
Using a 16-byte aligned structure achieves best results, both for code cleanliness and compiled code size. However, this means that we can't use the trick of encoding the slot number into the low 2 bits. Thankfully, we only ever use slot2, so make that explicit in the names of the relocation functions, and drop the code for other slots. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-s390: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-aarch64: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-arm: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-sparc: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ppc: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ppc64: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-i386: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-13 07:11:58 +0000