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2015-12-17cris: avoid "naked" qemu_logPaolo Bonzini
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17alpha: convert "naked" qemu_log to tracepointPaolo Bonzini
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17qemu-log: introduce qemu_log_separatePaolo Bonzini
In some cases, the same message is printed both on stderr and in the log. Avoid duplicate output in the default case where stderr _is_ the log, and standardize this to stderr+log where it used to use stdio+log. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17qemu-char: append opt to stop truncation of serial fileOlga Krishtal
Our QA team wants to preserve serial output of the guest in between QEMU runs to perform post-analysis. By default this behavior is off (file is truncated each time QEMU is started or device is plugged). Signed-off-by: Olga Krishtal <okrishtal@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Eric Blake <eblake@redhat.com> CC: Markus Armbruster <armbru@redhat.com> CC: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1449211324-17856-1-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17kvm: x86: add support for KVM_CAP_SPLIT_IRQCHIPPaolo Bonzini
This patch adds support for split IRQ chip mode. When KVM_CAP_SPLIT_IRQCHIP is enabled: 1.) The PIC, PIT, and IOAPIC are implemented in userspace while the LAPIC is implemented by KVM. 2.) The software IOAPIC delivers interrupts to the KVM LAPIC via kvm_set_irq. Interrupt delivery is configured via the MSI routing table, for which routes are reserved in target-i386/kvm.c then configured in hw/intc/ioapic.c 3.) KVM delivers IOAPIC EOIs via a new exit KVM_EXIT_IOAPIC_EOI, which is handled in target-i386/kvm.c and relayed to the software IOAPIC via ioapic_eoi_broadcast. Signed-off-by: Matt Gingell <gingell@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17kvm: add support for -machine kernel_irqchip=splitMatt Gingell
This patch adds the initial plumbing for split IRQ chip mode via KVM_CAP_SPLIT_IRQCHIP. In addition to option processing, a number of kvm_*_in_kernel macros are defined to help clarify which component is where. Signed-off-by: Matt Gingell <gingell@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17target-i386/kvm: Hyper-V SynIC timers MSR's supportAndrey Smetanin
Hyper-V SynIC timers are host timers that are configurable by guest through corresponding MSR's (HV_X64_MSR_STIMER*). Guest setup and use fired by host events(SynIC interrupt and appropriate timer expiration message) as guest clock events. The state of Hyper-V SynIC timers are stored in corresponding MSR's. This patch seria implements such MSR's support and migration. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Denis V. Lunev <den@openvz.org> CC: Roman Kagan <rkagan@virtuozzo.com> CC: kvm@vger.kernel.org Message-Id: <1448464885-8300-3-git-send-email-asmetanin@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17hw/misc: Hyper-V test device 'hyperv-testdev'Andrey Smetanin
'hyperv-testdev' will be used by kvm-unit-tests to setup Hyper-V SynIC SINT's routing and to inject Hyper-V SynIC SINT's. Hyper-V test device is ISA type device that creates 0x3000 IO memory region and catches write access into it. Every write operation data decoded into ctl code and parameters for Hyper-V test device. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17target-i386/hyperv: Hyper-V SynIC SINT routing and vcpu exitAndrey Smetanin
Hyper-V SynIC(synthetic interrupt controller) helpers for Hyper-V SynIC irq routing setup, irq injection, irq ack notifications event/message pages changes tracking for future use. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17kvm: Hyper-V SynIC irq routing supportAndrey Smetanin
Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17target-i386/kvm: Hyper-V SynIC MSR's supportAndrey Smetanin
This patch does Hyper-V Synthetic interrupt controller(Hyper-V SynIC) MSR's support and migration. Hyper-V SynIC is enabled by cpu's 'hv-synic' option. This patch does not allow cpu creation if 'hv-synic' option specified but kernel doesn't support Hyper-V SynIC. Changes v3: * removed 'msr_hv_synic_version' migration because it's value always the same * moved SynIC msr's initialization into kvm_arch_init_vcpu Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17linux-headers: update from kvm/nextPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Introduce 'x-disable-pcie' backword compatability propertyShmulik Ladkani
Following the previous patch which changed pvscsi to be a pci express device, this patch introduces a boolean property 'x-disable-pcie'. Its default value is false, exposing pvscsi as a pcie device. Setting 'x-disable-pcie' to 'on' preserves the old 'pci device' (non express) behavior. This allows migration to older versions. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-7-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: The pvscsi device is a PCIE endpointShmulik Ladkani
Report the 'express endpoint' capability if on a PCIE bus. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-6-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: coding: Introduce PVSCSIClassShmulik Ladkani
Introduce a class type for pvscsi, and the usual DEVICE_CLASS/DEVICE_GET_CLASS macros. No semantic change. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-5-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Introduce 'x-old-pci-configuration' backword compatability propertyShmulik Ladkani
Following the previous patches, which introduced various changes in pvscsi's pci configuration space (device subsystem id and revision, msi offset), this patch introduces a boolean property 'x-old-pci-configuration' to pvscsi. Its default value is false, exposing the above changes in the pci config space. Setting 'x-old-pci-configuration' to 'on' preserves the old behavior, which allows migration to older versions. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-4-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Change offset of msi pci capabilityShmulik Ladkani
Place device reported MSI capability at the same offset as placed by the VMware virtual hardware - at offset 0x7c. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-3-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Set device subsystem and revisionShmulik Ladkani
To be VMware PVSCSI SCSI Controller, rev 02. As reported by the VMware virtual hardware. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-2-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17memory: emulate ioeventfdPavel Fedin
The ioeventfd mechanism is used by vhost, dataplane, and virtio-pci to turn guest MMIO/PIO writes into eventfd file descriptor events. This allows arbitrary threads to be notified when the guest writes to a specific MMIO/PIO address. qtest and TCG do not support ioeventfd because memory writes are not checked against registered ioeventfds in QEMU. This patch implements this in memory_region_dispatch_write() so qtest can use ioeventfd. Also this patch fixes vhost aborting on some misconfigured old kernels like 3.18.0 on ARM. It is possible to explicitly enable CONFIG_EVENTFD in expert settings, while MMIO binding support in KVM will still be missing. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Message-Id: <006e01d12377$0b9c2d40$22d487c0$@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17kvm-all: PAGE_SIZE should be real host page sizeAndrew Jones
Just noticed this while grepping TARGET_PAGE_SIZE for an unrelated reason. I didn't use qemu_real_host_page_size as kvm_set_phys_mem() does, because we'd need to make sure page_size_init() has run first. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-Id: <1447115022-4142-1-git-send-email-drjones@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17exec: Remove unnecessary RAM_FILE flagEduardo Habkost
The only code that sets RAMBlock.fd is file_ram_alloc(), and the only code that calls file_ram_alloc() sets the RAM_FILE flag. That means the flag is always set when RAMBlock.fd >= 0, and the munmap() call at reclaim_ramblock() is dead code that never runs. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1446847881-9385-1-git-send-email-ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17memory: Eliminate memory_region_destructor_ram_from_ptr()Eduardo Habkost
The function is equivalent to memory_region_destructor_ram(), so it's not needed anymore. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1446844805-14492-3-git-send-email-ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17exec: Eliminate qemu_ram_free_from_ptr()Eduardo Habkost
Replace qemu_ram_free_from_ptr() with qemu_ram_free(). The only difference between qemu_ram_free_from_ptr() and qemu_ram_free() is that g_free_rcu() is used instead of call_rcu(reclaim_ramblock). We can safely replace it because: * RAM blocks allocated by qemu_ram_alloc_from_ptr() always have RAM_PREALLOC set; * reclaim_ramblock(block) will do nothing except g_free(block) if RAM_PREALLOC is set at block->flags. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1446844805-14492-2-git-send-email-ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20151217-1' into staging target-arm queue: * i.MX CCM patches * support guest debug for AArch64 KVM * support power button on virt board via GPIO * clean up AArch32 singlestep code * raise exception on misaligned LDREX operands * soc-dma: use hwaddr instead of target_ulong in printf * explicitly mark some ARM device loads as little-endian * i.MX: add support for lower and upper interrupt in GPIO # gpg: Signature made Thu 17 Dec 2015 13:38:09 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20151217-1: (25 commits) i.MX: Add an i.MX25 specific CCM class/instance i.MX: Split the CCM class into an abstract base class and a concrete class i.MX: rename i.MX CCM get_clock() function and CLK ID enum names i.MX: Fix i.MX31 default/reset configuration tests/guest-debug: introduce basic gdbstub tests target-arm: kvm - re-inject guest debug exceptions target-arm: kvm - add support for HW assisted debug target-arm: kvm - support for single step target-arm: kvm - implement software breakpoints target-arm: kvm64 - introduce kvm_arm_init_debug() ARM: Virt: Add gpio-keys node for Poweroff using DT ARM: Virt: Add QEMU powerdown notifier and hook it to GPIO Pin 3 ARM: ACPI: Add _E03 for Power Button ACPI: Add aml_gpio_int() wrapper for GPIO Interrupt Connection ACPI: Add GPIO Connection Descriptor ARM: ACPI: Add power button device in ACPI DSDT table ARM: ACPI: Add GPIO controller in ACPI DSDT table ARM: Virt: Add a GPIO controller acpi: extend aml_interrupt() to support multiple irqs acpi: support serialized method ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: Add an i.MX25 specific CCM class/instancepull-target-arm-20151217-1Jean-Christophe Dubois
With this CCM, i.MX25 timer is accurate with "real world time". Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 2c0cf90be767bfc8520661eca891ab22c61f18fe.1449528242.git.jcd@tribudubois.net Reviewed-by Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: Split the CCM class into an abstract base class and a concrete classJean-Christophe Dubois
The IMX_CCM class is now the base abstract class that is used by EPIT and GPT timer implementation. IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC. For now the i.MX25 continues to use the i.MX31 CCM implementation. An i.MX25 specific CCM will be introduced in a later patch. We also rework initialization to stop using deprecated sysbus device init. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: rename i.MX CCM get_clock() function and CLK ID enum namesJean-Christophe Dubois
This is to prepare for CCM code refactoring. This is just a bit of function and enum values renaming. We also remove some useless intermediate variables. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 53c4d9b9611988a5f56f178f285e04490747925e.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: Fix i.MX31 default/reset configurationJean-Christophe Dubois
Linux on i.MX31/KZM is expecting the CCM to use the CKIH ref clock instead of the CKIL plus the FPM multiplier. We change the CCMR reg reset value to match linux expected config. This allows the CCM to provide a 39MHz clk (as expected by linux) instead of the actual 50MHz. With this change the "sleep 60" command on linux is time accurate with "real world time". Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 6dc5bc4e0a450b20cecdb2991112e7281b653345.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17tests/guest-debug: introduce basic gdbstub testsAlex Bennée
The aim of these tests is to combine with an appropriate kernel image (with symbol-file vmlinux) and check it behaves as it should. Given a kernel it checks: - single step - software breakpoint - hardware breakpoint - access, read and write watchpoints On success it returns 0 to the calling process. I've not plumbed this into the "make check" logic though as we need a solution for providing non-host binaries to the tests. However the test is structured to work with pretty much any Linux kernel image as it uses the basic kernel_init code which is common across architectures. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1449599553-24713-7-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: kvm - re-inject guest debug exceptionsAlex Bennée
If we can't find details for the debug exception in our debug state then we can assume the exception is due to debugging inside the guest. To inject the exception into the guest state we re-use the TCG exception code (do_interrupt). However while guest debugging is in effect we currently can't handle the guest using single step as we will keep trapping to back to userspace. GDB makes heavy use of single-step behind the scenes which effectively means the guest's ability to debug itself is disabled while it is being debugged. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1449599553-24713-6-git-send-email-alex.bennee@linaro.org [PMM: Fixed a few typos in comments and commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: kvm - add support for HW assisted debugAlex Bennée
This adds basic support for HW assisted debug. The ioctl interface to KVM allows us to pass an implementation defined number of break and watch point registers. When KVM_GUESTDBG_USE_HW is specified these debug registers will be installed in place on the world switch into the guest. The hardware is actually capable of more advanced matching but it is unclear if this expressiveness is available via the gdbstub protocol. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1449599553-24713-5-git-send-email-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: kvm - support for single stepAlex Bennée
This adds support for single-step. There isn't much to do on the QEMU side as after we set-up the request for single step via the debug ioctl it is all handled within the kernel. The actual setting of the KVM_GUESTDBG_SINGLESTEP flag is already in the common code. If the kernel doesn't support guest debug the ioctl will simply error. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1449599553-24713-4-git-send-email-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: kvm - implement software breakpointsAlex Bennée
These don't involve messing around with debug registers, just setting the breakpoint instruction in memory. GDB will not use this mechanism if it can't access the memory to write the breakpoint. All the kernel has to do is ensure the hypervisor traps the breakpoint exceptions and returns to userspace. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1449599553-24713-3-git-send-email-alex.bennee@linaro.org [PMM: Fixed typo in comment] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: kvm64 - introduce kvm_arm_init_debug()Alex Bennée
As we haven't always had guest debug support we need to probe for it. Additionally we don't do this in the start-up capability code so we don't fall over on old kernels. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1449599553-24713-2-git-send-email-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: Virt: Add gpio-keys node for Poweroff using DTShannon Zhao
Add a gpio-keys node. This is used for Poweroff for the systems which use DT not ACPI. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-11-git-send-email-zhaoshenglong@huawei.com [PMM: use "standard-headers/linux/input.h" rather than <linux/input.h>] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: Virt: Add QEMU powerdown notifier and hook it to GPIO Pin 3Shannon Zhao
Currently mach-virt model doesn't support powerdown request. Guest VM doesn't react to system_powerdown from monitor console (or QMP) because there is no communication mechanism for such requests. This patch registers GPIO Pin 3 with powerdown notification. So guest VM can receive notification when such powerdown request is triggered. Signed-off-by: Wei Huang <wei@redhat.com> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: ACPI: Add _E03 for Power ButtonShannon Zhao
Here GPIO pin 3 is used for Power Button, add _E03 in ACPI DSDT table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ACPI: Add aml_gpio_int() wrapper for GPIO Interrupt ConnectionShannon Zhao
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1449804086-3464-8-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ACPI: Add GPIO Connection DescriptorShannon Zhao
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1449804086-3464-7-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: ACPI: Add power button device in ACPI DSDT tableShannon Zhao
Add power button device in ACPI DSDT table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: Wei Huang <wei@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1449804086-3464-6-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: ACPI: Add GPIO controller in ACPI DSDT tableShannon Zhao
Add GPIO controller in ACPI DSDT table. It can be used for gpio event. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-5-git-send-email-zhaoshenglong@huawei.com Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: Virt: Add a GPIO controllerShannon Zhao
ACPI 5.0 supports GPIO-signaled ACPI Events. This can be used for powerdown, hotplug evnets. Add a GPIO controller in machine virt, to support powerdown, maybe can be used for cpu hotplug. And here we use pl061. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17acpi: extend aml_interrupt() to support multiple irqsIgor Mammedov
ASL Interrupt() macro translates to Extended Interrupt Descriptor which supports variable number of IRQs. It will be used for conversion of ASL code for pc/q35 machines that use it for returning several IRQs in _PSR object. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1449804086-3464-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17acpi: support serialized methodXiao Guangrong
Add serialized method support so that explicit Mutex can be avoided Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1449804086-3464-2-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: Fix and improve AA32 singlestep translation completion codeSergey Fedorov
The AArch32 translation completion code for singlestep enabled/active case was a way more confusing and too repetitive then it needs to be. Probably that was the cause for a bug to be introduced into it at some point. The bug was that SWI/HVC/SMC exception would be generated in condition-failed instruction code path whereas it shouldn't. This patch rewrites the code in a way similar to the non-singlestep case. In the condition-passed/unconditional instruction code path we need to: - Write the condexec bits back to the CPU state - Advance the singlestep state machine and generate a corresponding exception in case of SWI/HVC/SMC - Write the PC back to the CPU state if it hasn't already been written and generate an appropriate singlestep exception otherwise In the condition-failed instruction code path we need to: - Set a TCG label to jump to it if the condition is failed - Write the condexec bits back to the CPU state - Write the PC back to the CPU state since it hasn't been written in this case - Generate an appropriate singlestep exception Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1448474560-22475-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann
Qemu does not generally perform alignment checks. However, the ARM ARM requires implementation of alignment exceptions for a number of cases including LDREX, and Windows-on-ARM relies on this. This change adds plumbing to enable alignment checks on loads using MO_ALIGN, a do_unaligned_access hook to raise the exception (data abort), and uses the new aligned loads in LDREX (for all but single-byte loads). Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1449167808-5656-1-git-send-email-Andrew.Baumann@microsoft.com [PMM: set WnR bits in syndrome and FSR as appropriate] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17arm: soc-dma: use hwaddr instead of target_ulong in printfPaolo Bonzini
This is a first baby step towards removing widespread inclusion of cpu.h and compiling more devices once (so that arm, aarch64 and in the future target-multi can share the object files). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: changed __FUNCTION__ to __func__ since we're touching these lines of code anyway] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17arm: explicitly mark device loads as little-endianPaolo Bonzini
Behaviour of emulated devices should not depend on the endianness of the CPU, so avoid using the endian-dependent load and store functions in the PXA2xx and OMAP display devices. These devices are little endian when they do DMA access. (Since ARM softmmu is always compiled as little endian, this means that the endian-dependent load and store functions are always little endian, so this commit makes no functionally visible change.) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: add support for lower and upper interrupt in GPIO.Jean-Christophe Dubois
The i.MX6 GPIO device supports 2 interrupts instead of one. * 1 for the lower 16 GPIOs. * 1 for the upper 16 GPIOs. i.MX31 and i.MX25 only support 1 interrupt for the 32 GPIOs. So we add a property to turn the behavior on when required. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1447497668-1603-1-git-send-email-jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17Merge remote-tracking branch 'remotes/kraxel/tags/pull-fw-cfg-20151217-1' ↵Peter Maydell
into staging fw_cfg: doc updates, various optimizations. # gpg: Signature made Thu 17 Dec 2015 08:59:32 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-fw-cfg-20151217-1: fw_cfg: replace ioport data read with generic method fw_cfg: add generic non-DMA read method fw_cfg: avoid calculating invalid current entry pointer fw_cfg: remove offset argument from callback prototype fw_cfg: amend callback behavior spec to once per select fw_cfg: move internal function call docs to header file Signed-off-by: Peter Maydell <peter.maydell@linaro.org>