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2016-02-19hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is providedv8-tzPeter Maydell
If the user passes us an EL3 boot rom, then it is going to want to implement the PSCI interface itself. In this case, disable QEMU's internal PSCI implementation so it does not get in the way, and instead start all CPUs in an SMP configuration at once (the boot rom will catch them all and pen up the secondaries until needed). The boot rom code is also responsible for editing the device tree to include any necessary information about its own PSCI implementation before eventually passing it to a NonSecure guest. (This "start all CPUs at once" approach is what both ARM Trusted Firmware and UEFI expect, since it is what the ARM Foundation Model does; the other approach would be to provide some emulated hardware for "start the secondaries" but this is simplest.) This is a compatibility break, but I don't believe that anybody was using a secure boot ROM with an SMP configuration. Such a setup would be somewhat broken since there was nothing preventing nonsecure guest code from calling the QEMU PSCI function to start up a secondary core in a way that completely bypassed the secure world. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-19target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell
Implement the performance monitor register traps controlled by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance registers already have an access function to deal with the user-enable bit, and the TPM checks can be added there. We also need a new access function which only implements the TPM checks for use by the few not-EL0-accessible registers and by PMUSERENR_EL0 (which is always EL0-readable). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-19target-arm: Fix handling of SDCR for 32-bit codePeter Maydell
Fix two issues with our implementation of the SDCR: * it is only present from ARMv8 onwards * it does not contain several of the trap bits present in its 64-bit counterpart the MDCR_EL3 Put the register description in the right place so that it does not get enabled for ARMv7 and earlier, and give it a write function so that we can mask out the bits which should not be allowed to have an effect if EL3 is 32-bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/arm/virt: Make first flash device Secure-only if booting securePeter Maydell
If the virt board is started with the 'secure' property set to request a Secure setup, then make the first flash device be visible only to the Secure world. This is a breaking change, but I don't expect it to be noticed by anybody, because running TZ-aware guests isn't common and those guests are generally going to be booting from the flash and implicitly expecting their Non-secure guests to not touch it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/arm/virt: Load bios image to MemoryRegion, not physaddrPeter Maydell
If we're loading a BIOS image into the first flash device, load it into the flash's memory region specifically, not into the physical address where the flash resides. This will make a difference when the flash might be in the Secure address space rather than the Nonsecure one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18loader: Add load_image_mr() to load ROM image to a MemoryRegionPeter Maydell
Add a new function load_image_mr(), which behaves like load_image_targphys() except that it loads the ROM image to a specified MemoryRegion rather than to a specified physical address. This is useful when a ROM blob needs to be loaded to a particular flash or ROM device but the address of that device in the machine's address space is not known. (For instance, ROMs in devices, or ROMs which might exist in a different address space to the system address space.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/arm/virt: Provide a secure-only RAM if booting in Secure modePeter Maydell
If we're booting in Secure mode, provide a secure-only RAM (just 16MB) so that secure firmware has somewhere to run from that won't be accessible to the Non-secure guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell
If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to NonSecure PL1 modes are illegal mode changes. Implement this check in bad_mode_switch(). (We don't currently implement HCR.TGE, but this is the only missing check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the rest of the HCR.TGE checks can be added later as necessary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-12-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell
Mode switches from Hyp to any other mode via the CPS and MRS instructions are illegal mode switches (though obviously switching via exception return is valid). Add this check to bad_mode_switch(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-11-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are given architected behaviour: * the mode field is unchanged * PSTATE.IL is set (so any subsequent instructions will UNDEF) * any other CPSR fields are written to as normal This is pretty much the same behaviour we picked for our UNPREDICTABLE handling, with the exception that for v8 we need to set the IL bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-10-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell
In v8 trying to switch mode to Mon from Secure EL1 is an illegal mode switch. (In v7 this is impossible as all secure modes except User are at EL3.) We can handle this case by making a switch to Mon valid only if the current EL is 3, which then gives the correct answer whether EL3 is AArch32 or AArch64. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-9-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell
We don't actually support Hyp mode yet, but add the correct checks for it to the bad_mode_switch() function for completeness. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-8-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Add comment about not implementing NSACR.RFRPeter Maydell
QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell
The only case where we can attempt a cpsr_write() mode switch from User is from the gdbstub; all other cases are handled in the calling code (notably translate.c). Architecturally attempts to alter the mode bits from user mode are simply ignored (and not treated as a bad mode switch, which in v8 sets CPSR.IL). Make mode switches from User ignored in cpsr_write() as well, for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-6-git-send-email-peter.maydell@linaro.org
2016-02-18linux-user: Use restrictive mask when calling cpsr_write()Peter Maydell
When linux-user code is calling cpsr_write(), use a restrictive mask to ensure we are limiting the set of CPSR bits we update. In particular, don't allow the mode bits to be changed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-5-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell
Raw CPSR writes should skip the architectural checks for whether we're allowed to set the A or F bits and should also not do the switching of register banks if the mode changes. Handle this inside cpsr_write(), which allows us to drop the "manually set the mode bits to avoid the bank switch" code from all the callsites which are using CPSRWriteRaw. This fixes a bug in 32-bit KVM handling where we had forgotten the "manually set the mode bits" part and could thus potentially trash the register state if the mode from the last exit to userspace differed from the mode on this exit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Add write_type argument to cpsr_write()Peter Maydell
Add an argument to cpsr_write() to indicate what kind of CPSR write is being requested, since the exact behaviour should differ for the different cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell
The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org
2016-02-18Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20160218-1' into staging target-arm queue: * implement or fix various EL3 trap behaviour for system registers * clean up the trap/undef handling of the SRS instruction * add some missing AArch64 performance monitor system registers * implement reset for the PL061 GPIO device * QOMify sd.c and the pxa2xx_mmci device * SD card emulation fixes for booting Tianocore UEFI on RPi2 * QOMify various ARM timer devices # gpg: Signature made Thu 18 Feb 2016 15:19:31 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160218-1: (36 commits) hw/timer: QOM'ify pxa2xx_timer hw/timer: QOM'ify pl031 hw/timer: QOM'ify exynos4210_rtc hw/timer: QOM'ify exynos4210_pwm hw/timer: QOM'ify exynos4210_mct hw/timer: QOM'ify arm_timer (pass 2) hw/timer: QOM'ify arm_timer (pass 1) hw/sd: use guest error logging rather than fprintf to stderr hw/sd: model a power-up delay, as a workaround for an EDK2 bug hw/sd: implement CMD23 (SET_BLOCK_COUNT) for MMC compatibility hw/sd/pxa2xx_mmci: Add reset function hw/sd/pxa2xx_mmci: Convert to VMStateDescription hw/sd/pxa2xx_mmci: Update to use new SDBus APIs hw/sd/pxa2xx_mmci: convert to SysBusDevice object sdhci_sysbus: Create SD card device in users, not the device itself hw/sd/sdhci.c: Update to use SDBus APIs hw/sd: Add QOM bus which SD cards plug in to hw/sd/sd.c: Convert sd_reset() function into Device reset method hw/sd/sd.c: QOMify hw/sd/sdhci.c: Remove x-drive property ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/timer: QOM'ify pxa2xx_timerpull-target-arm-20160218-1xiaoqiang.zhao
* split the old SysBus init function into an instance_init and a Device realize function * use DeviceClass::realize instead of SysBusDeviceClass::init Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/timer: QOM'ify pl031xiaoqiang.zhao
assign pl031_init to pl031_info.instance_init and drop the SysBusDeviceClass::init Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/timer: QOM'ify exynos4210_rtcxiaoqiang.zhao
assign exynos4210_rtc_init to exynos4210_rtc_info.instance_init and drop the SysBusDeviceClass::init Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/timer: QOM'ify exynos4210_pwmxiaoqiang.zhao
assign exynos4210_pwm_init to exynos4210_pwm_info.instance_init and drop the SysBusDeviceClass::init Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/timer: QOM'ify exynos4210_mctxiaoqiang.zhao
assign exynos4210_mct_init to exynos4210_mct_info.instance_init and drop the SysBusDeviceClass::init Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/timer: QOM'ify arm_timer (pass 2)xiaoqiang.zhao
assign DeviceClass::vmsd instead of using vmstate_register function Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/timer: QOM'ify arm_timer (pass 1)xiaoqiang.zhao
* assign icp_pit_init to icp_pit_info.instance_init * split the old SysBus init function into an instance_init and a Device realize function * use DeviceClass::realize instead of SysBusDeviceClass::init Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/sd: use guest error logging rather than fprintf to stderrAndrew Baumann
Some of these errors may be harmless (e.g. probing unimplemented commands, or issuing CMD12 in the wrong state), and may also be quite frequent. Spamming the standard error output isn't desirable in such cases. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1454902521-21164-4-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/sd: model a power-up delay, as a workaround for an EDK2 bugAndrew Baumann
The SD spec for ACMD41 says that a zero argument is an "inquiry" ACMD41, which does not start initialisation and is used only for retrieving the OCR. However, Tianocore EDK2 (UEFI) has a bug [1]: it first sends an inquiry (zero) ACMD41. If that first request returns an OCR value with the power up bit (0x80000000) set, it assumes the card is ready and continues, leaving the card in the wrong state. (My assumption is that this works on hardware, because no real card is immediately powered up upon reset.) This change models a delay of 0.5ms from the first ACMD41 to the power being up. However, it also immediately sets the power on upon seeing a non-zero (non-enquiry) ACMD41. This speeds up UEFI boot, it should also account for guests that simply delay after card reset and then issue an ACMD41 that they expect will succeed. [1] https://github.com/tianocore/edk2/blob/master/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c#L279 (This is the loop starting with "We need to wait for the MMC or SD card is ready") Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1454902521-21164-3-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/sd: implement CMD23 (SET_BLOCK_COUNT) for MMC compatibilityAndrew Baumann
CMD23 is optional for SD but required for MMC, and the UEFI bootloader used for Windows on Raspberry Pi 2 issues it. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1454902521-21164-2-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18hw/sd/pxa2xx_mmci: Add reset functionPeter Maydell
Add a reset function to the pxa2xx_mmci device; previously it had no handling for system reset at all. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1455646193-13238-11-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd/pxa2xx_mmci: Convert to VMStateDescriptionPeter Maydell
Convert the pxa2xx_mmci device from manual save/load functions to a VMStateDescription structure. This is a migration compatibility break. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1455646193-13238-10-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd/pxa2xx_mmci: Update to use new SDBus APIsPeter Maydell
Now the PXA2xx MMCI device is QOMified itself, we can update it to use the SDBus APIs to talk to the SD card. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455646193-13238-9-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd/pxa2xx_mmci: convert to SysBusDevice objectPeter Maydell
Convert the pxa2xx_mmci device to be a sysbus device. In this commit we only change the device itself, and leave the interface to the SD card using the old non-SDBus APIs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1455646193-13238-8-git-send-email-peter.maydell@linaro.org
2016-02-18sdhci_sysbus: Create SD card device in users, not the device itselfPeter Maydell
Move the creation of the SD card device from the sdhci_sysbus device itself into the boards that create these devices. This allows us to remove the cannot_instantiate_with_device_add notation because we no longer call drive_get_next in the device model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1455646193-13238-7-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd/sdhci.c: Update to use SDBus APIsPeter Maydell
Update the SDHCI code to use the new SDBus APIs. This commit introduces the new command line options required to connect a disk to sdhci-pci: -device sdhci-pci -drive id=mydrive,[...] -device sd,drive=mydrive Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1455646193-13238-6-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd: Add QOM bus which SD cards plug in toPeter Maydell
Add a QOM bus for SD cards to plug in to. Note that since sd_enable() is used only by one board and there only as part of a broken implementation, we do not provide it in the SDBus API (but instead add a warning comment about the old function). Whoever converts OMAP and the nseries boards to QOM will need to either implement the card switch properly or move the enable hack into the OMAP MMC controller model. In the SDBus API, the old-style use of sd_set_cb to register some qemu_irqs for notification of card insertion and write-protect toggling is replaced with methods in the SDBusClass which the card calls on status changes and methods in the SDClass which the controller can call to find out the current status. The query methods will allow us to remove the abuse of the 'register irqs' API by controllers in their reset methods to trigger the card to tell them about the current status again. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1455646193-13238-5-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd/sd.c: Convert sd_reset() function into Device reset methodPeter Maydell
Convert the sd_reset() function into a proper Device reset method. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1455646193-13238-4-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd/sd.c: QOMifyPeter Maydell
Turn the SD card into a QOM device. This conversion only changes the device itself; the various functions which are effectively methods on the device are not touched at this point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1455646193-13238-3-git-send-email-peter.maydell@linaro.org
2016-02-18hw/sd/sdhci.c: Remove x-drive propertyPeter Maydell
The following commits will remove support for the old sdhci-pci command line syntax using the x-drive property: -device sdhci-pci,x-drive=mydrive -drive id=mydrive,[...] and replace it with an explicit sd device: -device sdhci-pci -drive id=mydrive,[...] -device sd,drive=mydrive (This is OK because x-drive is experimental.) This commit removes the x-drive property so that old style command lines will fail with a reasonable error message: -device sdhci-pci,x-drive=mydrive: Property '.x-drive' not found Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1455646193-13238-2-git-send-email-peter.maydell@linaro.org
2016-02-18ARM: PL061: Cleaning field of PL061 device stateWei Huang
This patch removes the float_high field of PL061State, which doesn't seem to be used anywhere. Because this changes the device state, the version ID is also bumped up for the reason of compatiblity. Signed-off-by: Wei Huang <wei@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455729552-28026-3-git-send-email-wei@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18ARM: PL061: Clear PL061 device state after resetWei Huang
Current QEMU doesn't clear PL061 state after reset. This causes a weird issue with guest reboot via GPIO. Here is the device state with two reboot requests: (PL061State fields) data old_in_data istate VM boot 0 0 0 After 1st ACPI reboot request 8 8 8 After VM PL061 driver ACK 8 8 0 After VM reboot 8 8 0 ------------------------------------------------------------ 2nd ACPI reboot request 8 In the second reboot request above, because the old_in_data field is 8, QEMU decides that there is a pending edge IRQ already (see pl061_update()) in input; so it doesn't raise up IRQ again. As a result the second reboot request is lost. The correct way is to clear PL061 device state after reset. The default reset state is found from the documents listed below. Per Peter's suggestion that QEMU automatically calls reset function after device initialization, this patch removes calling pl061_reset() from pl061_initfn(). Reference: [1] PL061 Technical Reference Manual [2] Stellaris LM3S8962 Microcontroller Data Sheet [3] Stellaris LM3S5P31 Microcontroller Data Sheet Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1455729552-28026-2-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Add PMUSERENR_EL0 registerAlistair Francis
The Linux kernel accesses this register early in its setup. Signed-off-by: Christopher Covington <christopher.covington@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: b30d536cb16ec57b4412172bb6dbc3f00d293e7d.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Nathan Rossi <nathan@nathanrossi.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 50deeafb24958a5b6d7f594b5dda399a022c0e5b.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Nathan Rossi <nathan@nathanrossi.com> Message-id: da0563119a9f56fd5fbdc26e7ed19a8a8457c5b9.1455060548.git.alistair.francis@xilinx.com [PMM: Use 0 for PMCEID0 values for A15 and A57 since our PMU does not currently implement any events.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell
Make get_r13_banked() raise an exception at runtime for the corner case of SRS from System mode, so that we can UNDEF it; this brings us in to line with the ARM ARM's set of permitted CONSTRAINED UNPREDICTABLE choices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-18target-arm: Combine user-only and softmmu get/set_r13_banked()Peter Maydell
The user-mode versions of get/set_r13_banked() exist just to assert if they're ever called -- the translate time code should never emit calls to them because SRS from user mode always UNDEF. There's no code in the softmmu versions that can't compile in CONFIG_USER_ONLY, and the assertion is not particularly useful, so combine the two functions rather than having completely split versions under ifdefs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Move bank_number() into internals.hPeter Maydell
Move bank_number()'s implementation into internals.h, so it's available in the user-mode-only compile as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell
Move get/set_r13_banked() from helper.c to op_helper.c. This will let us add exception-raising code to them, and also puts them in the same file as get/set_user_reg(), which makes some conceptual sense. (The original reason for the helper.c/op_helper.c split was that only op_helper.c had access to the CPU env pointer; this distinction has not been true for a long time, though, and so the split is now rather arbitrary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-18target-arm: Clean up trap/undef handling of SRSPeter Maydell
The SRS instruction is: * UNDEFINED in Hyp mode * UNPREDICTABLE in User or System mode * UNPREDICTABLE if the specified mode isn't accessible * trapped to EL3 if EL3 is AArch64 and we are at Secure EL1 Clean up the code to handle all these cases cleanly, including picking UNDEF as our choice of UNPREDICTABLE behaviour rather blindly trusting the mode field passed in the instruction. As part of this, move the check for IS_USER into gen_srs() itself rather than having it done by the caller. The exception is that we don't UNDEF for calls from System mode, which need a runtime check. This will be dealt with in the following commits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-18target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, this should be reported with a syndrome register indicating an FP access trap, not one indicating a system register access trap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>