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2017-02-20stm32f205: Rename 'nvic' local to 'armv7m'v7m-qomifyPeter Maydell
The local variable 'nvic' in stm32f205_soc_realize() no longer holds a direct pointer to the NVIC device; it is a pointer to the ARMv7M container object. Rename it 'armv7m' accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20stm32f205: Create armv7m object without using armv7m_init()Peter Maydell
Switch the stm32f205 SoC to create the armv7m object directly rather than via the armv7m_init() wrapper. This fits better with the SoC model's very QOMified design. In particular this means we can push loading the guest image out to the top level board code where it belongs, rather than the SoC object having a QOM property for the filename to load. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Split systick out from NVICPeter Maydell
The SysTick timer isn't really part of the NVIC proper; we just modelled it that way back when we couldn't easily have devices that only occupied a small chunk of a memory region. Split it out into its own device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Don't put core v7M devices under CONFIG_STELLARISPeter Maydell
The NVIC is a core v7M device that exists for all v7M CPUs; put it under a CONFIG_ARM_V7M rather than hiding it under CONFIG_STELLARIS. (We'll use CONFIG_ARM_V7M for the SysTick device too when we split it out of the NVIC.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Make bitband device take the address space to accessPeter Maydell
Instead of the bitband device doing a cpu_physical_memory_read/write, make it take a MemoryRegion which specifies where it should be accessing, and use address_space_read/write to access the corresponding AddressSpace. Since this entails pretty much a rewrite, convert away from old_mmio in the process. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Make NVIC expose a memory region rather than mapping itselfPeter Maydell
Make the NVIC device expose a memory region for its users to map, rather than mapping itself into the system memory space on realize, and get the one user (the ARMv7M object) to do this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Make ARMv7M object take memory region linkPeter Maydell
Make the ARMv7M object take a memory region link which it uses to wire up the bitband rather than having them always put themselves in the system address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Use QOMified armv7m object in armv7m_init()Peter Maydell
Make the legacy armv7m_init() function use the newly QOMified armv7m object rather than doing everything by hand. We can return the armv7m object rather than the NVIC from armv7m_init() because its interface to the rest of the board (GPIOs, etc) is identical. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: QOMify the armv7m containerPeter Maydell
Create a proper QOM object for the armv7m container, which holds the CPU, the NVIC and the bitband regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Move NVICState struct definition into headerPeter Maydell
Move the NVICState struct definition into a header, so we can embed it into other QOM objects like SoCs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Abstract out the "load kernel" codePeter Maydell
Abstract the "load kernel" code out of armv7m_init() into its own function. This includes the registration of the CPU reset function, to parallel how we handle this for A profile cores. We make the function public so that boards which choose to directly instantiate an ARMv7M device object can call it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20cputlb: Don't assume do_unassigned_access() never returnsPeter Maydell
In get_page_addr_code(), if the guest PC doesn't correspond to RAM then we currently run the CPU's do_unassigned_access() hook if it has one, and otherwise we give up and exit QEMU with a more-or-less useful message. This code assumes that the do_unassigned_access hook will never return, because if it does then we'll plough on attempting to use a non-RAM TLB entry to get a RAM address and will abort() in qemu_ram_addr_from_host_nofail(). Unfortunately some CPU implementations of this hook do return: Microblaze, SPARC and the ARM v7M. Change the code to call report_bad_exec() if the hook returns, as well as if it didn't have one. This means we can tidy it up to use the cpu_unassigned_access() function which wraps the "get the CPU class and call the hook if it has one" work, since we aren't trying to distinguish "no hook" from "hook existed and returned" any more. This brings the handling of this hook into line with the handling used for data accesses, where "hook returned" is treated the same as "no hook existed" and gets you the default behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-02-20armv7m: Allow SHCSR writes to change pending and active bitsPeter Maydell
Implement the NVIC SHCSR write behaviour which allows pending and active status of some exceptions to be changed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Raise correct kind of UsageFault for attempts to execute ARM codePeter Maydell
M profile doesn't implement ARM, and the architecturally required behaviour for attempts to execute with the Thumb bit clear is to generate a UsageFault with the CFSR INVSTATE bit set. We were incorrectly implementing this as generating an UNDEFINSTR UsageFault; fix this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Check exception return consistencyPeter Maydell
Implement the exception return consistency checks described in the v7M pseudocode ExceptionReturn(). Inspired by a patch from Michael Davidsaver's series, but this is a reimplementation from scratch based on the ARM ARM pseudocode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Extract "exception taken" code into functionsPeter Maydell
Extract the code from the tail end of arm_v7m_do_interrupt() which enters the exception handler into a pair of utility functions v7m_exception_taken() and v7m_push_stack(), which correspond roughly to the pseudocode PushStack() and ExceptionTaken(). This also requires us to move the arm_v7m_load_vector() utility routine up so we can call it. Handling illegal exception returns has some cases where we want to take a UsageFault either on an existing stack frame or with a new stack frame but with a specific LR value, so we want to be able to call these without having to go via arm_v7m_cpu_do_interrupt(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLEMichael Davidsaver
The VECTCLRACTIVE and VECTRESET bits in the AIRCR are both documented as UNPREDICTABLE if you write a 1 to them when the processor is not halted in Debug state (ie stopped and under the control of an external JTAG debugger). Since we don't implement Debug state or emulated JTAG these bits are always UNPREDICTABLE for us. Instead of logging them as unimplemented we can simply log writes as guest errors and ignore them. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: change extracted from another patch; commit message constructed from scratch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-20armv7m: Simpler and faster exception startMichael Davidsaver
All the places in armv7m_cpu_do_interrupt() which pend an exception in the NVIC are doing so for synchronous exceptions. We know that we will always take some exception in this case, so we can just acknowledge it immediately, rather than returning and then immediately being called again because the NVIC has raised its outbound IRQ line. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: tweaked commit message; added DEBUG to the set of exceptions we handle immediately, since it is synchronous when it results from the BKPT instruction] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-20armv7m: Remove unused armv7m_nvic_acknowledge_irq() return valuePeter Maydell
Having armv7m_nvic_acknowledge_irq() return the new value of env->v7m.exception and its one caller assign the return value back to env->v7m.exception is pointless. Just make the return type void instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-20armv7m: Escalate exceptions to HardFault if necessaryMichael Davidsaver
The v7M exception architecture requires that if a synchronous exception cannot be taken immediately (because it is disabled or at too low a priority) then it should be escalated to HardFault (and the HardFault exception is then taken). Implement this escalation logic. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: extracted from another patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-20arm: gic: Remove references to NVICMichael Davidsaver
Now that the NVIC is its own separate implementation, we can clean up the GIC code by removing REV_NVIC and conditionals which use it. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-20armv7m: Fix condition check for taking exceptionsPeter Maydell
The M profile condition for when we can take a pending exception or interrupt is not the same as that for A/R profile. The code originally copied from the A/R profile version of the cpu_exec_interrupt function only worked by chance for the very simple case of exceptions being masked by PRIMASK. Replace it with a call to a function in the NVIC code that correctly compares the priority of the pending exception against the current execution priority of the CPU. [Michael Davidsaver's patchset had a patch to do something similar but the implementation ended up being a rewrite.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-20armv7m: Rewrite NVIC to not use any GIC codeMichael Davidsaver
Despite some superficial similarities of register layout, the M-profile NVIC is really very different from the A-profile GIC. Our current attempt to reuse the GIC code means that we have significant bugs in our NVIC. Implement the NVIC as an entirely separate device, to give us somewhere we can get the behaviour correct. This initial commit does not attempt to implement exception priority escalation, since the GIC-based code didn't either. It does fix a few bugs in passing: * ICSR.RETTOBASE polarity was wrong and didn't account for internal exceptions * ICSR.VECTPENDING was 16 too high if the pending exception was for an external interrupt * UsageFault, BusFault and MemFault were not disabled on reset as they are supposed to be Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: reworked, various bugs and stylistic cleanups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-20armv7m: Implement reading and writing of PRIGROUPPeter Maydell
Add a state field for the v7M PRIGROUP register and implent reading and writing it. The current NVIC doesn't honour the values written, but the new version will. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-20armv7m: Rename nvic_state to NVICStatePeter Maydell
Rename the nvic_state struct to NVICState, to match our naming conventions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-16Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* GUEST_PANICKED improvements (Anton) * vCont gdbstub rewrite (Claudio) * Fix CPU creation with -device (Liyang) * Logging fixes for pty chardevs (Ed) * Makefile "move if changed" fix (Lin) * First part of cpu_exec refactoring (me) * SVM emulation fix (me) * apic_delivered fix (Pavel) * "info ioapic" fix (Peter) * qemu-nbd socket activation (Richard) * QOMification of mcf_uart (Thomas) # gpg: Signature made Thu 16 Feb 2017 17:37:31 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (23 commits) target-i386: correctly propagate retaddr into SVM helpers vl: log available guest crash information report guest crash information in GUEST_PANICKED event i386/cpu: add crash-information QOM property Makefile: avoid leaving the temporary QEMU_PKGVERSION header file vl: Move the cpu_synchronize_all_post_init() after generic devices initialization qemu-nbd: Implement socket activation. qemu-doc: Clarify that -vga std is now the default cpu-exec: remove outermost infinite loop cpu-exec: avoid repeated sigsetjmp on interrupts cpu-exec: avoid cpu_loop_exit in cpu_handle_interrupt cpu-exec: tighten barrier on TCG_EXIT_REQUESTED cpu-exec: fix icount out-of-bounds access hw/char/mcf_uart: QOMify the ColdFire UART gdbstub: Fix vCont behaviour move vm_start to cpus.c char: drop data written to a disconnected pty apic: reset apic_delivered global variable on machine reset qemu-char: socket backend: disconnect on write error test-vmstate: remove yield_until_fd_readable ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-16target-i386: correctly propagate retaddr into SVM helpersPaolo Bonzini
Commit 2afbdf8 ("target-i386: exception handling for memory helpers", 2015-09-15) changed tlb_fill's cpu_restore_state+raise_exception_err to raise_exception_err_ra. After this change, the cpu_restore_state and raise_exception_err's cpu_loop_exit are merged into raise_exception_err_ra's cpu_loop_exit_restore. This actually fixed some bugs, but when SVM is enabled there is a second path from raise_exception_err_ra to cpu_loop_exit. This is the VMEXIT path, and now cpu_vmexit is called without a cpu_restore_state before. The fix is to pass the retaddr to cpu_vmexit (via cpu_svm_check_intercept_param). All helpers can now use GETPC() to pass the correct retaddr, too. Cc: qemu-stable@nongnu.org Fixes: 2afbdf84807d673eb682cb78158e11cdacbf4673 Reported-by: Alexander Boettcher <alexander.boettcher@genode-labs.com> Tested-by: Alexander Boettcher <alexander.boettcher@genode-labs.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/linux-user-for-upstream-pull-request' into staging # gpg: Signature made Thu 16 Feb 2017 14:35:46 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-upstream-pull-request: linux-user: Add FICLONE and FICLONERANGE ioctls linux-user: Use correct types in load_symbols() linux-user: fill target sigcontext struct accordingly linux-user: fix tcg/mmap test linux-user: fix settime old value location linux-user: Update m68k syscall definitions to match Linux 4.6 linux-user: Update sh4 syscall definitions to match Linux 4.8 linux-user: manage two new IFLA host message types linux-user: Fix mq_open linux-user: Fix readahead linux-user: Fix inotify_init1 support linux-user: Fix s390x safe-syscall for z900 linux-user: drop __cygwin__ ifdef linux-user: remove ifdef __USER_MISC Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-16vl: log available guest crash informationAnton Nefedov
There is a suitable log mask for the purpose. Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Message-Id: <1487053524-18674-4-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16report guest crash information in GUEST_PANICKED eventAnton Nefedov
it's not very convenient to use the crash-information property interface, so provide a CPU class callback to get the guest crash information, and pass that information in the event Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Message-Id: <1487053524-18674-3-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16i386/cpu: add crash-information QOM propertyAnton Nefedov
Windows reports BSOD parameters through Hyper-V crash MSRs. This information is very useful for initial crash analysis and thus it would be nice to have a way to fetch it. Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Message-Id: <1487053524-18674-2-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16Makefile: avoid leaving the temporary QEMU_PKGVERSION header fileLin Ma
By commit 67a1de0d, When we perform 'git pull && make && sudo make install', In 'make' stage a qemu-version.h.tmp will be generated. If the content of qemu-version.h.tmp and qemu-version.h aren't consistent, The qemu-version.h.tmp will be renamed to qemu-version.h. Because of the target FORCE, The same action will be do again in 'make install' stage. In 'make install' stage, If there is no qemu-version.h.tmp exists and we run 'make install' with sudo, The owner and group of new qemu-version.h.tmp will be privileged user/group. When we run 'make' next time, qemu-version.h.tmp can't be overwritten because of permission issue. This patch removed qemu-version.h.tmp after build to fix this issue. Signed-off-by: Lin Ma <lma@suse.com> Message-Id: <20170215024030.23895-1-lma@suse.com> Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16vl: Move the cpu_synchronize_all_post_init() after generic devices ↵Dou Liyang
initialization At the Qemu initialization, we call the cpu_synchronize_all_post_init() to synchronize All CPU states to KVM in the ./vl.c::main(). Currently, it is called before we initialize the CPUs, which is created by "-device" command and parsed by generic devices initialization, So, these CPUs may be ignored to synchronize. The patch moves the cpu_synchronize_all_post_init func after generic devices initialization to make sure that all the CPUs can be included. Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Message-Id: <1485916178-17838-1-git-send-email-douly.fnst@cn.fujitsu.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16qemu-nbd: Implement socket activation.Richard W.M. Jones
Socket activation (sometimes known as systemd socket activation) allows an Internet superserver to pass a pre-opened listening socket to the process, instead of having qemu-nbd open a socket itself. This is done via the LISTEN_FDS and LISTEN_PID environment variables, and a standard file descriptor range. This change partially implements socket activation for qemu-nbd. If the environment variables are set correctly, then socket activation will happen automatically, otherwise everything works as before. The limitation is that LISTEN_FDS must be 1. Signed-off-by: Richard W.M. Jones <rjones@redhat.com> Message-Id: <20170204100317.32425-2-rjones@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16linux-user: Add FICLONE and FICLONERANGE ioctlsHelge Deller
Add missing FICLONE and FICLONERANGE ioctls. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170211222602.GA6399@ls3530.fritz.box> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-16linux-user: Use correct types in load_symbols()Peter Maydell
Coverity doesn't like the code in load_symbols() which assumes it can use 'int' for a variable that might hold an offset into the guest ELF file, because in a 64-bit guest that could overflow. Guest binaries with 2GB sections aren't very likely and this isn't a security issue because we fully trust the guest linux-user binary anyway, but we might as well use the right types, which will placate Coverity. Use uint64_t to hold section sizes, and bail out if the symbol table is too large rather than just overflowing an int. (Coverity issue CID1005776) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1486249533-5260-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-16linux-user: fill target sigcontext struct accordinglyJose Ricardo Ziviani
A segfault is noticed when an emulated program uses any of ucontext regs fields. Risu detected this issue in the following operation when handling a signal: ucontext_t *uc = (ucontext_t*)uc; uc->uc_mcontext.regs->nip += 4; but this works fine: uc->uc_mcontext.gp_regs[PT_NIP] += 4; This patch set regs to a valid location as well as other sigcontext fields. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1485900317-3256-1-git-send-email-joserz@linux.vnet.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-16linux-user: fix tcg/mmap testMarc-André Lureau
tests/tcg/mmap test fails with values other than default target page size. When creating a map beyond EOF, extra anonymous pages are added up to the target page boundary. Currently, this operation is performed only when qemu_real_host_page_size < TARGET_PAGE_SIZE, but it should be performed if the configured page size (qemu -p) is larger than qemu_real_host_page_size too. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [pranith: dropped checkpatch changes] Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170119151533.29328-2-bobby.prani@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-16linux-user: fix settime old value locationMarc-André Lureau
old_value is the 4th argument of timer_settime(), not the 2nd. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170119151533.29328-1-bobby.prani@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-16linux-user: Update m68k syscall definitions to match Linux 4.6John Paul Adrian Glaubitz
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170116224915.19430-2-glaubitz@physik.fu-berlin.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-16linux-user: Update sh4 syscall definitions to match Linux 4.8John Paul Adrian Glaubitz
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170116223140.18634-2-glaubitz@physik.fu-berlin.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-16qemu-doc: Clarify that -vga std is now the defaultAlberto Garcia
The QEMU manual page states that Cirrus Logic is the default video card if the user doesn't specify any. However this is not true since QEMU 2.2. Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <20170127094154.19778-1-berto@igalia.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16cpu-exec: remove outermost infinite loopPaolo Bonzini
Reorganize the sigsetjmp so that the restart case falls through to cpu_handle_exception and the execution loop. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16cpu-exec: avoid repeated sigsetjmp on interruptsPaolo Bonzini
The sigsetjmp only needs to be prepared once for the whole execution of cpu_exec. This patch takes care of the "== 0" side, using a nested loop so that cpu_handle_interrupt goes straight back to cpu_handle_exception without doing another sigsetjmp. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16cpu-exec: avoid cpu_loop_exit in cpu_handle_interruptPaolo Bonzini
The siglongjmp goes straight back to the beginning of cpu_exec's outermost loop. We do not need a siglongjmp, we can simply leave the inner TB execution loop. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16cpu-exec: tighten barrier on TCG_EXIT_REQUESTEDPaolo Bonzini
This seems to have worked just fine so far on weakly-ordered architectures, but I don't see anything that prevents the reordering from: store 1 to exit_request store 1 to tcg_exit_req load tcg_exit_req store 0 to tcg_exit_req load exit_request store 0 to exit_request store 1 to exit_request store 1 to tcg_exit_req to this: store 1 to exit_request store 1 to tcg_exit_req load tcg_exit_req load exit_request store 1 to exit_request store 1 to tcg_exit_req store 0 to tcg_exit_req store 0 to exit_request therefore losing a request. It's possible that other memory barriers (e.g. in rcu_read_unlock) are hiding it, but better safe than sorry. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16cpu-exec: fix icount out-of-bounds accessPaolo Bonzini
When icount is active, tb_add_jump is surprisingly called with an out of bounds basic block index. I have no idea how that can work, but it does not seem like a good idea. Clear *last_tb for all TB_EXIT_ICOUNT_EXPIRED cases, even when all you have to do is refill icount_extra. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16hw/char/mcf_uart: QOMify the ColdFire UARTThomas Huth
Use type_init() etc. to adapt the ColdFire UART to the latest QEMU device conventions. Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <1485586582-6490-1-git-send-email-huth@tuxfamily.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16gdbstub: Fix vCont behaviourClaudio Imbrenda
When GDB issues a "vCont", QEMU was not handling it correctly when multiple VCPUs are active. For vCont, for each thread (VCPU), it can be specified whether to single step, continue or stop that thread. The default is to stop a thread. However, when (for example) "vCont;s:2" is issued, all VCPUs continue to run, although all but VCPU nr 2 are to be stopped. This patch completely rewrites the vCont parsing code. Please note that this improvement only works in system emulation mode, when in userspace emulation mode the old behaviour is preserved. Signed-off-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Message-Id: <1487092068-16562-3-git-send-email-imbrenda@linux.vnet.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-02-16move vm_start to cpus.cClaudio Imbrenda
This patch: * moves vm_start to cpus.c. * exports qemu_vmstop_requested, since it's needed by vm_start. * extracts vm_prepare_start from vm_start; it does what vm_start did, except restarting the cpus. * vm_start now calls vm_prepare_start and then restarts the cpus. Signed-off-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Message-Id: <1487092068-16562-2-git-send-email-imbrenda@linux.vnet.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>