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2021-02-15tests/qtest/sse-timer-test: Add simple test of the SSE timer devicesse-300Peter Maydell
Add a simple qtest to exercise the new timer device in the SSE-300. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15docs/system/arm/mps2.rst: Document the new mps3-an547 boardPeter Maydell
Add brief documentation of the new mps3-an547 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/mps2-tz: Add new mps3-an547 boardPeter Maydell
Add support for the mps3-an547 board; this is an SSE-300 based FPGA image that runs on the MPS3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/mps2-tz: Support running APB peripherals on different clockPeter Maydell
The AN547 runs the APB peripherals outside the SSE-300 on a different and slightly slower clock than it runs the SSE-300 with. Support making the APB peripheral clock frequency board-specific. (For our implementation only the UARTs actually take a clock.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/mps2-scc: Implement changes for AN547Peter Maydell
Implement the minor changes required to the SCC block for AN547 images: * CFG2 and CFG5 exist (like AN524) * CFG3 is reserved (like AN524) * CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this in the TODO comment Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/mps2-fpgaio: Support AN547 DBGCTRL registerPeter Maydell
For the AN547 image, the FPGAIO block has an extra DBGCTRL register, which is used to control the SPNIDEN, SPIDEN, NPIDEN and DBGEN inputs to the CPU. These signals control when the CPU permits use of the external debug interface. Our CPU models don't implement the external debug interface, so we model the register as reads-as-written. Implement the register, with a property defining whether it is present, and allow mps2-tz boards to specify that it is present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/mps2-fpgaio: Fold counters subsection into main vmstatePeter Maydell
We've already broken migration compatibility for all the MPS boards, so we might as well take advantage of this to simplify the vmstate for the FPGAIO device by folding the counters subsection into the main vmstate description. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/mps2-tz: Make UART overflow IRQ board-specificPeter Maydell
The AN547 puts the combined UART overflow IRQ at 48, not 47 like the other images. Make this setting board-specific. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Add SSE-300 supportPeter Maydell
Now we have sufficiently parameterised the code, we can add SSE-300 support by adding a new entry to the armsse_variants[] array. Note that the main watchdog (unlike the s32k watchdog) in the SSE-300 is a different device from the CMSDK watchdog; we don't have a model of it so we leave it as a TYPE_UNIMPLEMENTED_DEVICE stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL blockPeter Maydell
Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register block. Because this block is per-CPU and does not clash with any of the SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the existing has_cachectrl, has_cpusectrl and has_cpuid, rather than trying to add per-CPU-device support to the devinfo array handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfoPeter Maydell
The SSE-300 has four timers of type TYPE_SSE_TIMER; add support in the code for having these in an ARMSSEDeviceInfo array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfoPeter Maydell
The SSE-300 has a slightly different set of shared-per-CPU interrupts, allow the irq_is_common[] array to be different per SSE variant. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Add missing SSE-200 SYS_PPUPeter Maydell
We forgot to implement a TYPE_UNIMPLEMENTED_DEVICE stub for the SYS_PPU in the SSE-200, which is at 0x50022000. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Move PPUs into data-driven frameworkPeter Maydell
Move the PPUs into the data-driven device placement framework. We don't implement them, so they are just TYPE_UNIMPLEMENTED stubs. Because the SSE-200 and the IotKit diverge here (the IoTKit does not have the PPUs) we need to separate out the ARMSSEDeviceInfo for the two variants, and only add the PPUs to the SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Move sysctl register block into data-driven frameworkPeter Maydell
Move the sysctl register block into the data-driven device placement framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Move sysinfo register block into data-driven frameworkPeter Maydell
Move the sysinfo register block into the data-driven framework. While we are moving the code for configuring this device around, regularize on using &error_abortw when setting the integer properties: they are all simple DEFINE_PROP_UINT32 properties so the setting can never fail. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Move s32ktimer into data-driven frameworkPeter Maydell
Move the CMSDK timer that uses the S32K slow clock into the data-driven device placement framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Move watchdogs into data-driven frameworkPeter Maydell
Move the CMSDK watchdog device handling into the data-driven device placement framework. This is slightly more complicated because these devices might wire their IRQs up to the NMI line, and because one of them uses the slow 32KHz clock rather than the main clock. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Move dual-timer device into data-driven frameworkPeter Maydell
Move the CMSDK dualtimer device handling into the data-driven device placement framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Add framework for data-driven device placementPeter Maydell
The SSE-300 is mostly the same as the SSE-200, but it has moved some of the devices in the memory map and uses different device types in some cases. To accommodate this, add a framework where the placement and wiring of some devices can be specified in a data table. This commit adds the framework for this data-driven device placement, and makes the CMSDK APB timer devices use it. Subsequent commits will convert the other devices which differ between SSE-200 and SSE-300. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Add a define for number of IRQs used by the SSE itselfPeter Maydell
The SSE uses 32 interrupts for its own devices, and then passes through its expansion IRQ inputs to the CPU's interrupts 33 and upward. Add a define for the number of IRQs the SSE uses for itself, instead of hardcoding 32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Use an array for apb_ppc fields in the state structurePeter Maydell
Convert the apb_ppc0 and apb_ppc1 fields in the ARMSSE state struct to use an array instead of two separate fields. We already had one place in the code that wanted to be able to refer to the PPC by index, and we're about to add more code like that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register blockPeter Maydell
The SSE-300 has a new register block CPU<N>_PWRCTRL. There is one instance of this per CPU in the system (so just one for the SSE-300), and as well as the usual CIDR/PIDR ID registers it has just one register, CPUPWRCFG. This register allows the guest to configure behaviour of the system in power-down and deep-sleep states. Since QEMU does not model those, we make the register a dummy reads-as-written implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/miscPeter Maydell
The ARMSSE_CPUID and ARMSSE_MHU Kconfig stanzas are for the devices implmemented by hw/misc/cpuid.c and hw/misc/armsse-mhu.c. Move them to hw/misc/Kconfig where they belong. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register valuesPeter Maydell
The SSE-200 and SSE-300 have different PID register values from the IoTKit for the sysctl register block. We incorrectly implemented the SSE-200 with the same PID values as IoTKit. Fix the SSE-200 bug and report these register values for SSE-300. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registersPeter Maydell
The sysctl PDCM_PD_*_SENSE registers control various power domains in the system and allow the guest to configure which conditions keep a power domain awake and what power state to use when the domain is in a low power state. QEMU doesn't model power domains, so for us these registers are dummy reads-as-written implementations. The SSE-300 has a different power domain setup, so the set of registers is slightly different: Offset SSE-200 SSE-300 --------------------------------------------------- 0x200 PDCM_PD_SYS_SENSE PDCM_PD_SYS_SENSE 0x204 reserved PDCM_PD_CPU0_SENSE 0x208 reserved reserved 0x20c PDCM_PD_SRAM0_SENSE reserved 0x210 PDCM_PD_SRAM1_SENSE reserved 0x214 PDCM_PD_SRAM2_SENSE PDCM_PD_VMR0_SENSE 0x218 PDCM_PD_SRAM3_SENSE PDCM_PD_VMR1_SENSE Offsets 0x200 and 0x208 are the same for both, so handled in a previous commit; here we deal with 0x204, 0x20c, 0x210, 0x214, 0x218. (We can safely add new lines to the SSE300 vmstate because no board uses this device in an SSE300 yet.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL registerPeter Maydell
The SSE-300 has a new PWRCTRL register at offset 0x1fc (previously reserved). This register controls accessibility of some registers in the Power Policy Units (PPUs). Since QEMU doesn't implement the PPUs, we don't need to implement any real behaviour for this register, so we just handle the UNLOCK bit which controls whether writes to the register itself are permitted and otherwise make it be reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300Peter Maydell
The SSE-300 has only one CPU and so no INITSVTOR1. It does have INITSVTOR0, but unlike the SSE-200 this register now has a LOCK bit which can be set to 1 to prevent any further writes to the register. Implement these differences. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300Peter Maydell
In the SSE-300 the CPU_WAIT and NMI_ENABLE registers have moved offsets, so they are now where the SSE-200's WICCTRL and EWCTRL were. The SSE-300 does not have WICCTLR or EWCTRL at all, and the old offsets are reserved: Offset SSE-200 SSE-300 ----------------------------------- 0x118 CPUWAIT reserved 0x118 NMI_ENABLE reserved 0x120 WICCTRL CPUWAIT 0x124 EWCTRL NMI_ENABLE Handle this reshuffle, and the fact that SSE-300 has only one CPU and so only one active bit in CPUWAIT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviourPeter Maydell
The SSE-300's iokit-sysctl device is similar to the SSE-200, but some registers have moved address or have different behaviours. In this commit we add case statements for the registers where the SSE-300 and SSE-200 have the same behaviour. Some registers are the same on all SSE versions and so need no code change at all. Putting both of these categories together covers: 0x0 SECDBGSTAT 0x4 SECDBGSET 0x8 SECDBGCLR 0xc SCSECCTRL 0x10 CLK_CFG0 -- this is like SSE-200 FCLK_DIV but with a different set of clocks being controlled; our implementation is a dummy reads-as-written anyway 0x14 CLK_CFG1 -- similar to SSE-200 SYSCLK_DIV; our implementation is a dummy 0x18 CLK_FORCE -- similar to SSE-200 but different bit allocations; we have a dummy implementation 0x100 RESET_SYNDROME -- bit allocation differs from SSE-200 but our implementation is a dummy 0x104 RESET_MASK -- bit allocation differs from SSE-200 but our implementation is a dummy 0x108 SWRESET 0x10c GRETREG 0x200 PDCM_PD_SYS_SENSE -- some bit allocations differ, but our implementation is a dummy We also need to migrate the state of these registers which are shared between the SSE-200 and SSE-300, so update the vmstate 'needed' function to do this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/timer/sse-timer.c: Model the SSE subsystem System TimerPeter Maydell
The SSE-300 includes some timers which are a different kind to those in the SSE-200. Model them. These timers are documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDRPeter Maydell
For SSE-300, the SYSINFO register block has two new registers: * SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3; since the SSE-300 can only be configured with a single CPU it is always zero * IIDR is the subsystem implementation identity register; its value is set by the SoC integrator, so we plumb this in from the armsse.c code as we do with SYS_VERSION and SYS_CONFIG Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300Peter Maydell
In the SSE-300, the format of the SYS_CONFIG0 register has changed again; pass through the correct value to the SYSINFO register block device. We drop the old SysConfigFormat enum, which was implemented in the hope that different flavours of SSE would share the same format; since they all seem to be different and we now have an sse_version enum to key off, just use that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register valuesPeter Maydell
The version of the SYSINFO Register Block in the SSE-300 has different CIDR/PIDR register values to the SSE-200; pass in the sse-version property and use it to select the correct ID register values. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-secctl.c: Implement SSE-300 PID register valuesPeter Maydell
The versions of the Secure Access Configuration Register Block and Non-secure Access Configuration Register Block in the SSE-300 are the same as those in the SSE-200, but the CIDR/PIDR ID register values are different. Plumb through the sse-version property and use it to select the correct ID register values. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/misc/iotkit-sysctl: Remove is_sse200 flagPeter Maydell
Remove the is_sse200 flag in favour of just directly testing the new sse_version field. Since some of these registers exist in the SSE-300 but some do not or have different behaviour, we expand out the if() statements in the read and write functions into switch()es, so we have an easy place to put SSE-300 specific behaviour. (Until we do add the SSE-300 behaviour, the thing preventing us reaching the "unreachable" default cases is that armsse.c doesn't yet pass us an ARMSSE_SSE300 version.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/armsse: Introduce SSE subsystem version propertyPeter Maydell
We model Arm "Subsystems for Embedded" SoC subsystems using generic code which is split into various sub-devices which are configurable by QOM properties to handle the behaviour differences between the SSE subsystems we implement. Currently the only sub-device which needs to change is the IOTKIT_SYSCTL device, and we do this with a mix of properties that directly specify divergent behaviours (eg CPUWAIT_RST) and passing it the SYS_VERSION register value as a way for it to distinguish IoTKit from SSE-200. The "pass SYS_VERSION" approach is already a bit hacky, since the IOTKIT_SYSCTL device has to know that the different part of the register value happens to be bits [31:28]. For SSE-300 this register is renamed SOC_IDENTITY and has a different format entirely, all of whose fields can be configured by the SoC integrator when they integrate the SSE into their SoC, and so "pass SYS_VERSION" breaks down completely. Switch to using a simple integer property representing an internal-to-QEMU enumeration of the SSE flavour. For the moment we only need this in IOTKIT_SYSCTL, but as we add SSE-300 support a few of the other devices will also need to know. We define and permit a value for the SSE-300 so we can start using it in subsequent commits which add SSE-300 support. The now-redundant is_sse200 flag in IoTKitSysCtl will be removed in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- I didn't use a full-on qdev/QOM 'enum' property here because that requires messing with the QAPI schema, which seems like overkill for this entirely-internal-to-the-implementation bit of information passing.
2021-02-15hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()Peter Maydell
Use the new clock_ns_to_ticks() function in npcm7xx_timer where appropriate. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com>
2021-02-15clock: Add clock_ns_to_ticks() functionPeter Maydell
Add a clock_ns_to_ticks() function which does the opposite of clock_ticks_to_ns(): given a duration in nanoseconds, it returns the number of clock ticks that would happen in that time. This is useful for devices that have a free running counter register whose value can be calculated when it is read. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Hao Wu <wuhaotsh@google.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-15clock: Add ClockPreUpdate callback event typePeter Maydell
Add a new callback event type ClockPreUpdate, which is called on period changes before the period is updated. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-15clock: Add ClockEvent parameter to callbacksPeter Maydell
The Clock framework allows users to specify a callback which is called after the clock's period has been updated. Some users need to also have a callback which is called before the clock period is updated. As the first step in adding support for notifying Clock users on pre-update events, add an argument to the ClockCallback to specify what event is being notified, and add an argument to the various functions for registering a callback to specify which events are of interest to that callback. Note that the documentation update renders correct the previously incorrect claim in 'Adding a new clock' that callbacks "will be explained in a following section". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> --- v2->v3: used 'unsigned int' instead of 'int' for parameters and struct fields containing an event mask, as suggested by Philippe; fixed events argument to qdev_init_clock_in() with NULL callback pointer in npcm7xx_adc.c (spotted by Hao)
2021-02-15hw/arm/mps2: Update old infocenter.arm.com URLsPeter Maydell
Update old infocenter.arm.com URLs to the equivalent developer.arm.com ones (the old URLs should redirect, but we might as well avoid the redirection notice, and the new URLs are pleasantly shorter). This commit covers the links to the MPS2 board TRM, the various Application Notes, the IoTKit and SSE-200 documents. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- There are some other infocenter URLs in the codebase; we should probably update those too, but they don't really fit in with this patchset, so I'll do them separately later. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-15docs/system/arm/mps2.rst: Document the new mps3-an524 boardPeter Maydell
Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-15hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524Peter Maydell
The AN524 has a PL031 RTC, which we have a model of; provide it rather than an unimplemented-device stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-15hw/arm/mps2-tz: Stub out USB controller for mps3-an524Peter Maydell
The AN524 has a USB controller (an ISP1763); we don't have a model of it but we should provide a stub "unimplemented-device" for it. This is slightly complicated because the USB controller shares a PPC port with the ethernet controller. Implement a make_* function which provides creates a container MemoryRegion with both the ethernet controller and an unimplemented-device stub for the USB controller. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-15hw/arm/mps2-tz: Add new mps3-an524 boardPeter Maydell
Add support for the mps3-an524 board; this is an SSE-200 based FPGA image, like the existing mps2-an521. It has a usefully larger amount of RAM, and a PL031 RTC, as well as some more minor differences. In real hardware this image runs on a newer generation of the FPGA board, the MPS3 rather than the older MPS2. Architecturally the two boards are similar, so we implement the MPS3 boards in the mps2-tz.c file as variations of the existing MPS2 boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfoPeter Maydell
The armv7m_load_kernel() function takes a mem_size argument which it expects to be the size of the memory region at guest address 0. (It uses this argument only as a limit on how large a raw image file it can load at address zero). Instead of hardcoding this value, find the RAMInfo corresponding to the 0 address and extract its size. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-15hw/arm/mps2-tz: Support ROMs as well as RAMsPeter Maydell
The AN505 and AN521 don't have any read-only memory, but the AN524 does; add a flag to ROMInfo to mark a region as ROM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo dataPeter Maydell
Instead of hardcoding the MachineClass default_ram_size and default_ram_id fields, set them on class creation by finding the entry in the RAMInfo array which is marked as being the QEMU system RAM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-15hw/arm/mps2-tz: Make RAM arrangement board-specificPeter Maydell
The AN505 and AN521 have the same layout of RAM; the AN524 does not. Replace the current hard-coding of where the RAM is and which parts of it are behind which MPCs with a data-driven approach. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>