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2021-02-08migration: Add blocker informationDr. David Alan Gilbert
Modify query-migrate so that it has a flag indicating if outbound migration is blocked, and if it is a list of reasons. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20210202135522.127380-2-dgilbert@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration: Fix a few absurdly defective error messagesMarkus Armbruster
migrate_params_check() has a number of error messages of the form Parameter 'NAME' expects is invalid, it should be ... Fix them to something like Parameter 'NAME' expects a ... Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20210202141734.2488076-5-armbru@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration: Fix cache_init()'s "Failed to allocate" error messagesMarkus Armbruster
cache_init() attempts to handle allocation failure. The two error messages are garbage, as untested error messages commonly are: Parameter 'cache size' expects Failed to allocate cache Parameter 'cache size' expects Failed to allocate page cache Fix them to just Failed to allocate cache Failed to allocate page cache Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20210202141734.2488076-4-armbru@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration: Clean up signed vs. unsigned XBZRLE cache-sizeMarkus Armbruster
73af8dd8d7 "migration: Make xbzrle_cache_size a migration parameter" (v2.11.0) made the new parameter unsigned (QAPI type 'size', uint64_t in C). It neglected to update existing code, which continues to use int64_t. migrate_xbzrle_cache_size() returns the new parameter. Adjust its return type. QMP query-migrate-cache-size returns migrate_xbzrle_cache_size(). Adjust its return type. migrate-set-parameters passes the new parameter to xbzrle_cache_resize(). Adjust its parameter type. xbzrle_cache_resize() passes it on to cache_init(). Adjust its parameter type. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20210202141734.2488076-3-armbru@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration: Fix migrate-set-parameters argument validationMarkus Armbruster
Commit 741d4086c8 "migration: Use proper types in json" (v2.12.0) switched MigrationParameters to narrower integer types, and removed the simplified qmp_migrate_set_parameters()'s argument checking accordingly. Good idea, except qmp_migrate_set_parameters() takes MigrateSetParameters, not MigrationParameters. Its job is updating migrate_get_current()->parameters (which *is* of type MigrationParameters) according to its argument. The integers now get truncated silently. Reproducer: ---> {'execute': 'query-migrate-parameters'} <--- {"return": {[...] "compress-threads": 8, [...]}} ---> {"execute": "migrate-set-parameters", "arguments": {"compress-threads": 257}} <--- {"return": {}} ---> {'execute': 'query-migrate-parameters'} <--- {"return": {[...] "compress-threads": 1, [...]}} Fix by resynchronizing MigrateSetParameters with MigrationParameters. Fixes: 741d4086c856320807a2575389d7c0505578270b Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20210202141734.2488076-2-armbru@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration: introduce 'userfaultfd-wrlat.py' scriptAndrey Gruzdev
Add BCC/eBPF script to analyze userfaultfd write fault latency distribution. Signed-off-by: Andrey Gruzdev <andrey.gruzdev@virtuozzo.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20210129101407.103458-6-andrey.gruzdev@virtuozzo.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration: implementation of background snapshot threadAndrey Gruzdev
Introducing implementation of 'background' snapshot thread which in overall follows the logic of precopy migration while internally utilizes completely different mechanism to 'freeze' vmstate at the start of snapshot creation. This mechanism is based on userfault_fd with wr-protection support and is Linux-specific. Signed-off-by: Andrey Gruzdev <andrey.gruzdev@virtuozzo.com> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20210129101407.103458-5-andrey.gruzdev@virtuozzo.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration: support UFFD write fault processing in ram_save_iterate()Andrey Gruzdev
In this particular implementation the same single migration thread is responsible for both normal linear dirty page migration and procesing UFFD page fault events. Processing write faults includes reading UFFD file descriptor, finding respective RAM block and saving faulting page to the migration stream. After page has been saved, write protection can be removed. Since asynchronous version of qemu_put_buffer() is expected to be used to save pages, we also have to flush migraion stream prior to un-protecting saved memory range. Write protection is being removed for any previously protected memory chunk that has hit the migration stream. That's valid for pages from linear page scan along with write fault pages. Signed-off-by: Andrey Gruzdev <andrey.gruzdev@virtuozzo.com> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20210129101407.103458-4-andrey.gruzdev@virtuozzo.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> fixup pagefault.address cast for 32bit
2021-02-08migration: introduce UFFD-WP low-level interface helpersAndrey Gruzdev
Glue code to the userfaultfd kernel implementation. Querying feature support, createing file descriptor, feature control, memory region registration, IOCTLs on registered registered regions. Signed-off-by: Andrey Gruzdev <andrey.gruzdev@virtuozzo.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20210129101407.103458-3-andrey.gruzdev@virtuozzo.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Fixed up range.start casting for 32bit
2021-02-08migration: introduce 'background-snapshot' migration capabilityAndrey Gruzdev
Add new capability to 'qapi/migration.json' schema. Update migrate_caps_check() to validate enabled capability set against introduced one. Perform checks for required kernel features and compatibility with guest memory backends. Signed-off-by: Andrey Gruzdev <andrey.gruzdev@virtuozzo.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210129101407.103458-2-andrey.gruzdev@virtuozzo.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08migration/qemu-file: Fix maybe uninitialized on qemu_get_buffer_in_place()Wainer dos Santos Moschetta
Fixed error when compiling migration/qemu-file.c with -Werror=maybe-uninitialized as shown here: ../migration/qemu-file.c: In function 'qemu_get_buffer_in_place': ../migration/qemu-file.c:604:18: error: 'src' may be used uninitialized in this function [-Werror=maybe-uninitialized] 604 | *buf = src; | ~~~~~^~~~~ cc1: all warnings being treated as errors Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20210128130625.569900-1-wainersm@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08savevm: Fix memory leak of vmstate_configurationJinhao Gao
When VM migrate VMState of configuration, the fields(name and capabilities) of configuration having a flag of VMS_ALLOC need to allocate memory. If the src doesn't free memory of capabilities in SaveState after save VMState of configuration, or the dst doesn't free memory of name and capabilities in post load of configuration, it may result in memory leak of name and capabilities. We free memory in configuration_post_save and configuration_post_load func, which prevents memory leak. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Jinhao Gao <gaojinhao@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20201231061020.828-3-gaojinhao@huawei.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08spapr_pci: Fix memory leak of vmstate_spapr_pciJinhao Gao
When VM migrate VMState of spapr_pci, the field(msi_devs) of spapr_pci having a flag of VMS_ALLOC need to allocate memory. If the src doesn't free memory of msi_devs in SaveStateEntry of spapr_pci after QEMUFile save VMState of spapr_pci, it may result in memory leak of msi_devs. We add the post_save func to free memory, which prevents memory leak. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Jinhao Gao <gaojinhao@huawei.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20201231061020.828-2-gaojinhao@huawei.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-02-08Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210207' ↵Peter Maydell
into staging qemu-sparc queue # gpg: Signature made Sun 07 Feb 2021 22:09:12 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20210207: utils/fifo8: add VMSTATE_FIFO8_TEST macro utils/fifo8: change fatal errors from abort() to assert() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-07utils/fifo8: add VMSTATE_FIFO8_TEST macroMark Cave-Ayland
Rewrite the existing VMSTATE_FIFO8 macro to use VMSTATE_FIFO8_TEST as per the standard pattern in include/migration/vmstate.h. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210128221728.14887-3-mark.cave-ayland@ilande.co.uk>
2021-02-07utils/fifo8: change fatal errors from abort() to assert()Mark Cave-Ayland
Developer errors are better represented with assert() rather than abort(). Also improve the strictness of the checks by using range checks within the assert() rather than converting the existing equality checks to inequality checks. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210121102518.20112-1-mark.cave-ayland@ilande.co.uk>
2021-02-05Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210205' ↵Peter Maydell
into staging TCGCPUOps cleanups (claudio) tcg/s390 compare fix (phil) tcg/aarch64 rotli_vec fix tcg/tci cleanups and fixes # gpg: Signature made Fri 05 Feb 2021 22:55:10 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210205: (46 commits) accel: introduce AccelCPUClass extending CPUClass accel: replace struct CpusAccel with AccelOpsClass accel: extend AccelState and AccelClass to user-mode cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass cpu: move debug_check_watchpoint to tcg_ops cpu: move adjust_watchpoint_address to tcg_ops physmem: make watchpoint checking code TCG-only cpu: move do_unaligned_access to tcg_ops cpu: move cc->transaction_failed to tcg_ops cpu: move cc->do_interrupt to tcg_ops target/arm: do not use cc->do_interrupt for KVM directly cpu: Move debug_excp_handler to tcg_ops cpu: Move tlb_fill to tcg_ops cpu: Move cpu_exec_* to tcg_ops cpu: Move synchronize_from_tb() to tcg_ops accel/tcg: split TCG-only code from cpu_exec_realizefn target/riscv: remove CONFIG_TCG, as it is always TCG cpu: Introduce TCGCpuOperations struct tcg/tci: Remove TCG_CONST tcg/tci: Fix TCG_REG_R4 misusage ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-05accel: introduce AccelCPUClass extending CPUClassClaudio Fontana
add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. This will allow to separate the target cpu code that is specific to each accelerator, and register it automatically with object hierarchy lookup depending on accelerator code availability, as part of the accel_init_interfaces() initialization step. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-19-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05accel: replace struct CpusAccel with AccelOpsClassClaudio Fontana
This will allow us to centralize the registration of the cpus.c module accelerator operations (in accel/accel-softmmu.c), and trigger it automatically using object hierarchy lookup from the new accel_init_interfaces() initialization step, depending just on which accelerators are available in the code. Rename all tcg-cpus.c, kvm-cpus.c, etc to tcg-accel-ops.c, kvm-accel-ops.c, etc, matching the object type names. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-18-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05accel: extend AccelState and AccelClass to user-modeClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [claudio: rebased on Richard's splitwx work] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-17-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana
we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move debug_check_watchpoint to tcg_opsClaudio Fontana
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and commit 3826121d9298 ("target-arm: Implement checking of fired") introduced an ARM-specific hack for cpu_check_watchpoint. Make debug_check_watchpoint optional, and move it to tcg_ops. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-15-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move adjust_watchpoint_address to tcg_opsClaudio Fontana
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs") introduced this ARM-specific, TCG-specific hack to adjust the address, before checking it with cpu_check_watchpoint. Make adjust_watchpoint_address optional and move it to tcg_ops. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-14-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05physmem: make watchpoint checking code TCG-onlyClaudio Fontana
cpu_check_watchpoint, watchpoint_address_matches are TCG-only. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-13-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana
make it consistently SOFTMMU-only. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: make the field presence in cpu.h unconditional, removing the ifdefs] Message-Id: <20210204163931.7358-12-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY] avoiding its use in headers used by common_ss code (should be poisoned). Note: need to be careful with the use of CONFIG_USER_ONLY, Message-Id: <20210204163931.7358-11-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-10-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05target/arm: do not use cc->do_interrupt for KVM directlyClaudio Fontana
cc->do_interrupt is in theory a TCG callback used in accel/tcg only, to prepare the emulated architecture to take an interrupt as defined in the hardware specifications, but in reality the _do_interrupt style of functions in targets are also occasionally reused by KVM to prepare the architecture state in a similar way where userspace code has identified that it needs to deliver an exception to the guest. In the case of ARM, that includes: 1) the vcpu thread got a SIGBUS indicating a memory error, and we need to deliver a Synchronous External Abort to the guest to let it know about the error. 2) the kernel told us about a debug exception (breakpoint, watchpoint) but it is not for one of QEMU's own gdbstub breakpoints/watchpoints so it must be a breakpoint the guest itself has set up, therefore we need to deliver it to the guest. So in order to reuse code, the same arm_do_interrupt function is used. This is all fine, but we need to avoid calling it using the callback registered in CPUClass, since that one is now TCG-only. Fortunately this is easily solved by replacing calls to CPUClass::do_interrupt() with explicit calls to arm_do_interrupt(). Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210204163931.7358-9-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move debug_excp_handler to tcg_opsEduardo Habkost
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-8-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost
[claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-7-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-6-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG, reworded comments] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-5-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05accel/tcg: split TCG-only code from cpu_exec_realizefnClaudio Fontana
move away TCG-only code, make it compile only on TCG. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-4-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana
for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-3-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded struct for now, to make code conversion easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: move TCGCpuOperations inside include/hw/core/cpu.h] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-2-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TCG_CONSTRichard Henderson
Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Fix TCG_REG_R4 misusageRichard Henderson
This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still present in the array, and adjust the numbers in the interpreter. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Restrict TCG_TARGET_NB_REGS to 16Richard Henderson
As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TODO as unusedRichard Henderson
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Implement 64-bit divisionRichard Henderson
Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*Richard Henderson
We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Use g_assert_not_reachedRichard Henderson
Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_{st_i32,st32_i64}Richard Henderson
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Move stack bounds check to compile-timeRichard Henderson
The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_st16_{i32,i64}Richard Henderson
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_st8_{i32,i64}Richard Henderson
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}Richard Henderson
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld16s_{i32,i64}Richard Henderson
Eliminating a TODO for ld16s_i64. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld16u_{i32,i64}Richard Henderson
Eliminating a TODO for ld16u_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld8s_{i32,i64}Richard Henderson
Eliminating a TODO for ld8s_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-14 23:44:37 +0000