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2018-02-15raspi: Raspberry Pi 3 supportpull-target-arm-20180215-1Pekka Enberg
This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The differences to Pi 2 are: - Firmware address - Board ID - Board revision The CPU is different too, but that's going to be configured as part of the machine default CPU when we introduce a new machine type. The patch was written from scratch by me but the logic is similar to Zoltán Baldaszti's previous work, which I used as a reference (with permission from the author): https://github.com/bztsrc/qemu-raspi3 Signed-off-by: Pekka Enberg <penberg@iki.fi> [PMM: fixed trailing whitespace on one line] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15bcm2836: Make CPU type configurablePekka Enberg
This patch adds a "cpu-type" property to BCM2836 SoC in preparation for reusing the code for the Raspberry Pi 3, which has a different processor model. Signed-off-by: Pekka Enberg <penberg@iki.fi> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell
The v8M architecture includes hardware support for enforcing stack pointer limits. We don't implement this behaviour yet, but provide the MSPLIM and PSPLIM stack pointer limit registers as reads-as-written, so that when we do implement the checks in future this won't break guest migration. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-12-peter.maydell@linaro.org
2018-02-15target/arm: Migrate v7m.other_spPeter Maydell
In commit abc24d86cc0364f we accidentally broke migration of the stack pointer value for the mode (process, handler) the CPU is not currently running as. (The commit correctly removed the no-longer-used v7m.current_sp flag from the VMState but also deleted the still very much in use v7m.other_sp SP value field.) Add a subsection to migrate it again. (We don't need to care about trying to retain compatibility with pre-abc24d86cc0364f versions of QEMU, because that commit bumped the version_id and we've since bumped it again a couple of times.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-11-peter.maydell@linaro.org
2018-02-15target/arm: Add AIRCR to vmstate structPeter Maydell
In commit commit 3b2e934463121 we added support for the AIRCR register holding state, but forgot to add it to the vmstate structs. Since it only holds r/w state if the security extension is implemented, we can just add it to vmstate_m_security. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-10-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversionsPeter Maydell
In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>, NVIC_IABR<n> -- in all these cases we were missing the "* 8" needed to convert from the byte offset to the interrupt number (since all these registers use one bit per interrupt) * writes of NVIC_IPR<n> had the opposite problem of a spurious "* 8" (since these registers use one byte per interrupt) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180209165810.6668-9-peter.maydell@linaro.org
2018-02-15target/arm: Implement writing to CONTROL_NS for v8MPeter Maydell
In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-8-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement SCRPeter Maydell
We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell
M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection Register (CSSELR) The only difference is that they're in the NVIC memory mapped register space rather than being coprocessor registers. Implement the M profile view of them. Since neither Cortex-M3 nor Cortex-M4 implement caches, we don't need to update their init functions and can leave the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. Newer cores (like the Cortex-M33) will want to be able to set these ID registers to non-zero values, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-6-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement v8M CPPWR registerPeter Maydell
The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-5-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement M profile cache maintenance opsPeter Maydell
For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-4-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handlingPeter Maydell
The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-3-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVICPeter Maydell
Instead of hardcoding the values of M profile ID registers in the NVIC, use the fields in the CPU struct. This will allow us to give different M profile CPU types different ID register values. This commit includes the addition of the missing ID_ISAR5, which exists as RES0 in both v7M and v8M. (The values of the ID registers might be wrong for the M4 -- this commit leaves the behaviour there unchanged.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-2-peter.maydell@linaro.org
2018-02-15target/arm: Handle SVE registers when using clear_vec_highRichard Henderson
When storing to an AdvSIMD FP register, all of the high bits of the SVE register are zeroed. Therefore, call it more often with is_q as a parameter. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Enforce access to ZCR_EL at translationRichard Henderson
This also makes sure that we get the correct ordering of SVE vs FP exceptions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Suppress TB end for FPCR/FPSRRichard Henderson
Nothing in either register affects the TB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Enforce FP access to FPCR/FPSRRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Remove ARM_CP_64BIT from ZCR_EL registersRichard Henderson
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.ioPhilippe Mathieu-Daudé
(qemu) info mtree address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom - 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io + 000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180209085755.30414-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15hw/arm/aspeed: directly map the serial device to the system address spacePhilippe Mathieu-Daudé
(qemu) info mtree address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io - 000000001e784000-000000001e78401f (prio 0, i/o): serial 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 [...] 000000001e720000-000000001e728fff (prio 0, ram): aspeed.sram 000000001e782000-000000001e782fff (prio 0, i/o): aspeed.timer + 000000001e784000-000000001e78401f (prio 0, i/o): serial 000000001e785000-000000001e78501f (prio 0, i/o): aspeed.wdt 000000001e785020-000000001e78503f (prio 0, i/o): aspeed.wdt Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180209085755.30414-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request v2: * Dropped Fam's git-publish series because there is still ongoing discussion # gpg: Signature made Thu 15 Feb 2018 09:42:03 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: misc: fix spelling ratelimit: don't align wait time with slices vl: pause vcpus before stopping iothreads Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15Merge remote-tracking branch 'remotes/huth/tags/pull-request-2018-02-14' ↵Peter Maydell
into staging Various improvements to the qtest checks: - Clean-ups by Eric Blake with regards to the global_qtest variable - Some more test cases for the boot-serial tester - Re-activation of the m48t59-test # gpg: Signature made Wed 14 Feb 2018 11:07:44 GMT # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" # gpg: aka "Thomas Huth <thuth@redhat.com>" # gpg: aka "Thomas Huth <huth@tuxfamily.org>" # gpg: aka "Thomas Huth <th.huth@posteo.de>" # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth/tags/pull-request-2018-02-14: tests/m48t59: Use the m48t59 test on ppc, too tests/Makefile: Derive check-qtest-ppc64-y from check-qtest-ppc-y tests/m48t59: Make the test independent of global_qtest tests/m48t59: Fix and re-enable the test for sparc tests/boot-serial-test: Add support for the aarch64 virt machine tests/boot-serial: Add tests for PowerPC Mac machines tests/boot-serial: Enable the boot-serial test on SPARC machines, too wdt_ib700-test: Drop dependence on global_qtest tests/boot-sector: Drop dependence on global_qtest qmp-test: Drop dependence on global_qtest libqos: Use explicit QTestState for remaining libqos operations libqos: Use explicit QTestState for ahci operations libqos: Use explicit QTestState for i2c operations libqos: Use explicit QTestState for rtas operations libqos: Use explicit QTestState for fw_cfg operations libqos: Track QTestState with QPCIBus libqtest: Use qemu_strtoul() tests: Clean up wait for event Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Wed 14 Feb 2018 10:37:02 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: m68k: implement movep instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15misc: fix spellingMarc-André Lureau
s/pupulate/populate Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180208162447.10851-1-marcandre.lureau@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-02-15ratelimit: don't align wait time with slicesWolfgang Bumiller
It is possible for rate limited writes to keep overshooting a slice's quota by a tiny amount causing the slice-aligned waiting period to effectively halve the rate. Signed-off-by: Wolfgang Bumiller <w.bumiller@proxmox.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Message-id: 20180207071758.6818-1-w.bumiller@proxmox.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-02-15vl: pause vcpus before stopping iothreadsStefan Hajnoczi
Commit dce8921b2baaf95974af8176406881872067adfa ("iothread: Stop threads before main() quits") introduced iothread_stop_all() to avoid the following virtio-scsi assertion failure: assert(blk_get_aio_context(d->conf.blk) == s->ctx); Back then the assertion failed because when bdrv_close_all() made d->conf.blk NULL, blk_get_aio_context() returned the global AioContext instead of s->ctx. The same assertion can still fail today when vcpus submit new I/O requests after iothread_stop_all() has moved the BDS to the global AioContext. This patch hardens the iothread_stop_all() approach by pausing vcpus before calling iothread_stop_all(). Note that the assertion failure is a race condition. It is not possible to reproduce it reliably. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180201110708.8080-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-02-14tests/m48t59: Use the m48t59 test on ppc, tooThomas Huth
The ref405ep machine has a memory-mapped m48t59 device, so we can run the m48t59 test on this machine, too. Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/Makefile: Derive check-qtest-ppc64-y from check-qtest-ppc-yThomas Huth
ppc64 is a superset of ppc, so the ppc64 tests should include all the ppc tests. Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/m48t59: Make the test independent of global_qtestThomas Huth
Stop using the functions that require global_qtest here and pass around the QTestState instead (global_qtest should finally get removed since this causes problems with tests running in parallel). Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/m48t59: Fix and re-enable the test for sparcThomas Huth
The m48t59 test has been disabled in commit baeddded5fe6fa37d13fb94bf8d ("sparc: disable qtest in make check"), likely due to some timing issues in the bcd_check_time tests which might fail if it gets interrupted for too long. It should be OK to re-enable this test if we make sure that we do not run it on timing-sensitive machines, thus it should be OK if we only run it in the g_test_slow() mode. Additionally, there are two other issues: First, the test can not run so easily on sparc64 anymore, since commit f3b18f35a23c60edbda6420cd ("sun4u: switch m48t59 NVRAM to MMIO access") moved the m48t59 device to the ebus instead, and for this you first have to set up the corresponding PCI device (which is currently not possible from within the m48t59 test). So we can only re-enable this test on sparc, but not the sparc64 target. Second, the fuzzing test is executed before the bcd-check-time test (due to the naming of the tests), without having the base address set up properly, so the fuzzing test does not really check anything at all. Fix it by setting up the base address from the main function already and by moving the qtest_start() to the tests themselves, so that each test starts with a clean environment (since after the fuzzing, the clock is unusable for the bcd-check-time test). Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-serial-test: Add support for the aarch64 virt machineWei Huang
This patch adds a small binary kernel to test aarch64 virt machine's UART. Signed-off-by: Wei Huang <wei@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> [thuth: Fixed contextual conflicts with the hppa and sdhci patches] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-serial: Add tests for PowerPC Mac machinesThomas Huth
OpenBIOS prints out the CPU type on these machine types, so we can use this string to test whether the CPU detection is working correctly. Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-serial: Enable the boot-serial test on SPARC machines, tooThomas Huth
OpenBIOS prints out the name of the detected CPU here, so looking for this string is a nice test to verify that the CPU detection is still working correctly. Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14wdt_ib700-test: Drop dependence on global_qtestEric Blake
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Improve this test to be explicit about the state. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-sector: Drop dependence on global_qtestEric Blake
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Adjust the helper code to use explicit state instead, and update all callers. Fix some trailing whitespace while touching the file. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14qmp-test: Drop dependence on global_qtestEric Blake
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Although qmp-test does not maintain parallel qtest connections, it was the last test assigning to global_qtest. It's just as easy to be explicit about the state; once all tests have been cleaned up, a later patch can then get rid of global_qtest and a layer of wrappers in libqtest. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for remaining libqos operationsEric Blake
Drop one more client of global_qtest by teaching all remaining libqos stragglers to pass in an explicit QTestState. Change the setting of global_qtest from being implicit in libqos' call to qtest_start() to instead be explicit in all clients that are still relying on global_qtest. Note that qmp_execute() can be greatly simplified in the process, and that we also get rid of interpolation of a JSON string into a temporary variable when qtest_qmp() can do it more reliably. Signed-off-by: Eric Blake <eblake@redhat.com> Acked-by: Greg Kurz <groug@kaod.org> Reviewed-by: John Snow <jsnow@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for ahci operationsEric Blake
Drop one more client of global_qtest by teaching all ahci test functionality to pass in an explicit QTestState. The state was already available, so no callers had to be adjusted. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for i2c operationsEric Blake
Drop one more client of global_qtest by teaching all i2c test functionality to pass in an explicit QTestState, adjusting all callers. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for rtas operationsEric Blake
Drop one more client of global_qtest by teaching all rtas test functionality to pass in an explicit QTestState, adjusting all callers. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Use nicer indentation in rtas.h] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for fw_cfg operationsEric Blake
Drop one more client of global_qtest by teaching all fw_cfg test functionality (invoked through alloc-pc) to pass in an explicit QTestState, adjusting all callers. In particular, fw_cfg-test had to reorder things to create the test state prior to creating the fw_cfg (and drop a pointless strdup in the meantime), but that test now no longer depends on global_qtest. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Fixed conflict wrt pc_alloc_init() in vhost-user-test.c] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Track QTestState with QPCIBusEric Blake
When initializing a QPCIBus, track which QTestState the bus is associated with (so that a later patch can then explicitly use that test state for all communication on the bus, rather than blindly relying on global_qtest). Update the initialization functions to take another parameter, and update all callers to pass in state (for now, most callers get away with passing the current global_qtest as the current state, although this required fixing the order of initialization to ensure qtest_start() is called before qpci_init*() in rtl8139-test, and provided an opportunity to pass in the allocator in e1000e-test). Touch up some allocations to use g_new0() rather than g_malloc() while in the area, and simplify some code (all implementations of QOSOps provide a .init_allocator() that never fails). Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Removed hunk from vhost-user-test.c that is not required anymore, fixed conflict in qtest_vboot() and adjusted qpci_init_pc() in sdhci-test] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14m68k: implement movep instructionPavel Dovgalyuk
This patch implements movep instruction. It moves data between a data register and alternate bytes within the address space starting at the location specified and incrementing by two. It was designed for the original 68000 and used in firmwares for interfacing the 8-bit peripherals through the 16-bit data bus. Without this patch opcode for this instruction is recognized as some bitop. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Mihail Abakumov <mikhail.abakumov@ispras.ru> Tested-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180206124431.31433.91946.stgit@pasha-VirtualBox> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-02-14libqtest: Use qemu_strtoul()Eric Blake
This will keep checkpatch happy when the next patch does code motion. Fix the include order to match HACKING when adding the needed header. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests: Clean up wait for eventMarkus Armbruster
We still use hacks like qmp("") to wait for an event, even though we have qmp_eventwait() since commit 8fe941f, and qmp_eventwait_ref() since commit 7ffe312. Both commits neglected to convert all the existing hacks. Make up what they missed. Bonus: gets rid of empty format strings. A step towards compile-time format string checking without triggering -Wformat-zero-length. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com> [thuth: dropped the hunks from the usb tests - not needed anymore] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-13Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches # gpg: Signature made Tue 13 Feb 2018 17:03:11 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (55 commits) iotests: Add l2-cache-entry-size to iotest 137 iotests: Test downgrading an image using a small L2 slice size iotests: Test valid values of l2-cache-entry-size qcow2: Allow configuring the L2 slice size qcow2: Rename l2_table in count_cow_clusters() qcow2: Rename l2_table in count_contiguous_clusters_unallocated() qcow2: Rename l2_table in count_contiguous_clusters() qcow2: Rename l2_table in qcow2_alloc_compressed_cluster_offset() qcow2: Update qcow2_truncate() to support L2 slices qcow2: Update expand_zero_clusters_in_l1() to support L2 slices qcow2: Prepare expand_zero_clusters_in_l1() for adding L2 slice support qcow2: Read refcount before L2 table in expand_zero_clusters_in_l1() qcow2: Update qcow2_update_snapshot_refcount() to support L2 slices qcow2: Prepare qcow2_update_snapshot_refcount() for adding L2 slice support qcow2: Update zero_single_l2() to support L2 slices qcow2: Update discard_single_l2() to support L2 slices qcow2: Update handle_alloc() to support L2 slices qcow2: Update handle_copied() to support L2 slices qcow2: Update qcow2_alloc_cluster_link_l2() to support L2 slices qcow2: Update qcow2_get_cluster_offset() to support L2 slices ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-13Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* CAN bus (will be under network maintainner) * scsi-block opblockers (myself) * Dirty log bitmap cleanup (myself) * SDHCI improvements and tests (Philippe) * HAX support for larger guest sizese (Yu Ning) # gpg: Signature made Tue 13 Feb 2018 15:37:14 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (48 commits) travis: use libgcc-4.8-dev (libgcc-6-dev is not available on Ubuntu 14.04) memory: unify loops to sync dirty log bitmap memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshot memory: remove memory_region_test_and_clear_dirty g364fb: switch to using DirtyBitmapSnapshot sdhci: add Spec v4.2 register definitions sdhci: add a check_capab_v3() qtest sdhci: check Spec v3 capabilities qtest hw/arm/xilinx_zynqmp: enable the UHS-I mode hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet hw/arm/fsl-imx6: implement SDHCI Spec. v3 hw/arm/bcm2835_peripherals: change maximum block size to 1kB hw/arm/bcm2835_peripherals: implement SDHCI Spec v3 sdhci: implement CMD/DAT[] fields in the Present State register sdhci: implement UHS-I voltage switch sdbus: add trace events sdhci: implement the Host Control 2 register (tuning sequence) sdhci: rename the hostctl1 register sdhci: add support for v3 capabilities hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-13Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio,vhost,pci,pc: features, fixes and cleanups - new stats in virtio balloon - virtio eventfd rework for boot speedup - vhost memory rework for boot speedup - fixes and cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 13 Feb 2018 16:29:55 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (22 commits) virtio-balloon: include statistics of disk/file caches acpi-test: update FADT lpc: drop pcie host dependency tests: acpi: fix FADT not being compared to reference table hw/pci-bridge: fix pcie root port's IO hints capability libvhost-user: Support across-memory-boundary access libvhost-user: Fix resource leak virtio-balloon: unref the memory region before continuing pci: removed the is_express field since a uniform interface was inserted virtio-blk: enable multiple vectors when using multiple I/O queues pci/bus: let it has higher migration priority pci-bridge/i82801b11: clear bridge registers on platform reset vhost: Move log_dirty check vhost: Merge and delete unused callbacks vhost: Clean out old vhost_set_memory and friends vhost: Regenerate region list from changed sections list vhost: Merge sections added to temporary list vhost: Simplify ring verification checks vhost: Build temporary section list and deref after commit virtio: improve virtio devices initialization time ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-13virtio-balloon: include statistics of disk/file cachesTomáš Golembiovský
Signed-off-by: Tomáš Golembiovský <tgolembi@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-02-13acpi-test: update FADTMichael S. Tsirkin
Previous commit ("tests: acpi: fix FADT not being compared to reference table") started tracking changes to the FADT. Generate the expected FACP files - apparently these weren't updated since 2013. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 16:36:22 +0000