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2017-01-09hw/arm/virt: Add board property to enable EL2gicv3-virtPeter Maydell
Add a board level property to the virt board which will enable EL2 on the CPU if the user asks for it. The default is not to provide EL2. If EL2 is enabled then we will use SMC as our PSCI conduit, and report the virtualization support in the GICv3 device tree node and the ACPI tables. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com>
2017-01-09target-arm: Enable EL2 feature bit on A53 and A57Peter Maydell
Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and Cortex-A57, since this is all now sufficiently implemented to work with the GICv3. We provide the usual CPU property to disable it for backwards compatibility with the older virt boards. In this commit, we disable the EL2 feature on the virt and ZynpMP boards, so there is no overall effect. Another commit will expose a board-level property to allow the user to enable EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
2017-01-09target/arm/psci.c: If EL2 implemented, start CPUs in EL2Peter Maydell
The PSCI spec states that a CPU_ON call should cause the new CPU to be started in the highest implemented Non-secure exception level. We were incorrectly starting it at the exception level of the caller, which happens to be correct if EL2 is not implemented. Implement the correct logic as described in the PSCI 1.0 spec section 6.4: * if EL2 exists and SCR_EL3.HCE is set: start in EL2 * otherwise start in EL1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: use SMC if booting in EL2Andrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> [PMM: look at vms->psci_conduit rather than vms->virt to decide whether to use HVC or SMC, and report no PSCI support at all for the 'PSCI disabled' case] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: Support using SMC for PSCIPeter Maydell
If we are giving the guest a CPU with EL2, it is likely to want to use the HVC instruction itself, for instance for providing PSCI to inner guest VMs. This makes using HVC as the PSCI conduit for the outer QEMU a bad idea. We will want to use SMC instead is this case: this makes sense because QEMU's PSCI implementation is effectively an emulation of functionality provided by EL3 firmware. Add code to support selecting the PSCI conduit to use, rather than hardcoding use of HVC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Andrew Jones <drjones@redhat.com>
2017-01-09hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regsPeter Maydell
Implement the architecturally required traps from NS EL1 to EL2 for the CPU interface registers. These fall into several different groups: * group-0-only registers all trap if ICH_HRC_EL2.TALL0 is set (exactly the registers covered by gicv3_fiq_access()) * group-1-only registers all trap if ICH_HRC_EL2.TALL1 is set (exactly the registers covered by gicv3_irq_access()) * DIR traps if ICH_HCR_EL2.TC or ICH_HCR_EL2.TDIR are set * PMR, RPR, CTLR trap if ICH_HCR_EL2.TC is set * SGI0R, SGI1R, ASGI1R trap if ICH_HCR_EL2.TC is set or if HCR_EL2.IMO or HCR_EL2.FMO are set We split DIR and the SGI registers out into their own access functions, leaving the existing gicv3_irqfiq_access() just handling PMR, RPR and CTLR. This commit doesn't implement support for trapping on HSTR_EL2.T12 for the 32-bit registers, as we don't implement any of those per-coprocessor trap bits currently and probably will want to do those in some more centralized way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()Peter Maydell
Implement the function which signals virtual interrupts to the CPU as appropriate following CPU interface state changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IARPeter Maydell
Implement the two remaining ICV_ registers: EOIR and IAR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registersPeter Maydell
Implement the the ICV_ registers HPPIR, DIR and RPR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/intc/arm_gicv3: Implement ICV_ registers which are just accessorsPeter Maydell
If the HCR_EL2.IMO or FMO bits are set, accesses to ICC_ system registers are redirected to be accesses to ICV_ registers (the guest-visible interface to the virtual interrupt controller). Implement this behaviour for the ICV_ registers which are simple accessors to the underlying register state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/intc/arm_gicv3: Add accessors for ICH_ system registersPeter Maydell
The GICv3 virtualization interface includes system registers accessible only to the hypervisor which form the control interface for interrupt virtualization. Implement these registers. The function gicv3_cpuif_virt_update() which determines whether it needs to signal vIRQ, vFIQ or a maintenance interrupt is introduced here as a stub function -- its implementation will be added in a subsequent commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/intc/gicv3: Add data fields for virtualization supportPeter Maydell
As the first step in adding support for the virtualization extensions to the GICv3 emulation: * add the necessary data fields to the state structures * add the fields to the migration state, as a subsection which is only present if virtualization is enabled The use of a subsection means we retain migration compatibility as EL2 is not enabled on any CPUs currently. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/intc/gicv3: Add defines for ICH system register fieldsPeter Maydell
Add defines to gicv3_internal.h for fields in the ICH_* system registers which form the GIC virtualization control interface. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09target-arm: Add ARMCPU fields for GIC CPU i/f configPeter Maydell
Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPUPeter Maydell
Wire the new VIRQ, VFIQ and maintenance interrupt lines from the GIC to each CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09target-arm: Expose output GPIO line for VCPU maintenance interruptPeter Maydell
The GICv3 support for virtualization includes an outbound maintenance interrupt signal which is asserted when the CPU interface wants to signal to the hypervisor that it needs attention. Expose this as an outbound GPIO line from the CPU object which can be wired up as a physical interrupt line by the board code (as we do already for the CPU timers). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-01-09hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQPeter Maydell
Augment the GIC's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. We never use these, but it's helpful to keep the v2-and-earlier GIC's external interface in line with that of the GICv3 to avoid board code having to add extra code conditional on which version of the GIC is in use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
2017-01-09hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQPeter Maydell
Augment the GICv3's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20170109' into staging target-arm queue: * i2c: Allow I2C devices to NAK start events * hw/char: QOM'ify exynos4210_uart.c * clean up and refactor virt-acpi-build.c * virt-acpi-build: Don't incorrectly claim architectural timer to be edge-triggered * m25p80: Don't let rogue SPI controllers cause buffer overruns * imx_spi: Remove broken MSGDATA register support # gpg: Signature made Mon 09 Jan 2017 11:52:49 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170109: (21 commits) hw/ssi/imx_spi.c: Remove MSGDATA register support m25p80: don't let rogue SPI controllers cause buffer overruns hw/arm/virt-acpi-build: Don't incorrectly claim architectural timer to be edge-triggered hw/arm/virt: remove VirtGuestInfo hw/arm/virt-acpi-build: don't save VirtGuestInfo on AcpiBuildState hw/arm/virt-acpi-build: remove redundant members from VirtGuestInfo hw/arm/virt: pass VirtMachineState instead of VirtGuestInfo hw/arm/virt: move VirtMachineState/Class to virt.h hw/arm/virt: remove include/hw/arm/virt-acpi-build.h hw/arm/virt: eliminate struct VirtGuestInfoState hw/arm/virt: use VirtMachineState.gic_version hw/arm/virt: parameter passing cleanups hw/arm/virt-acpi-build: fadt: improve flag naming hw/arm/virt-acpi-build: gtdt: improve flag naming hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriately hw/arm/virt-acpi-build: add all missing cpu_to_le's hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered hw/arm/virt: Rename 'vbi' variables to 'vms' hw/arm/virt: Merge VirtBoardInfo and VirtMachineState hw/char: QOM'ify exynos4210_uart.c ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/ssi/imx_spi.c: Remove MSGDATA register supportpull-target-arm-20170109Jean-Christophe Dubois
From the documentation it is not clear what this SPI register is about. Moreover, neither linux driver nor xvisor driver are using this SPI register. For now we just remove it and issue a log on register write access. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 20170107122047.26300-1-jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09m25p80: don't let rogue SPI controllers cause buffer overrunsJean-Christophe Dubois
In normal operation we should never attempt to put more data into the data[] array than it can hold. However if the SPI controller connected to us misbehaves then it can send us a sequence of commands that attempt this. Since the controller might be in the guest (if the hardware does SPI via bit-banging), catch the possible overrun conditions and reset the flash internal state, logging them as guest errors. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 20170107111631.24444-1-jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: rewrote commit message to be more exact about when this can happen] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: Don't incorrectly claim architectural timer to be ↵Andrew Jones
edge-triggered This is the ACPI equivalent to "hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered" which fixes the DT for machine types 2.9 and later. Signed-off-by: Andrew Jones <drjones@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-15-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: remove VirtGuestInfoAndrew Jones
by moving VirtGuestInfo.fw_cfg to VirtMachineState. This is the mach-virt equivalent of "pc: Move PcGuestInfo.fw_cfg to PCMachineState" and "pc: Eliminate PcGuestInfo struct" combined. Signed-off-by: Andrew Jones <drjones@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-14-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: don't save VirtGuestInfo on AcpiBuildStateAndrew Jones
We can get to VirtMachineState without the need for saving a pointer on AcpiBuildState. This is the mach-virt equivalent to "acpi: Don't save PcGuestInfo on AcpiBuildState" Signed-off-by: Andrew Jones <drjones@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-13-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: remove redundant members from VirtGuestInfoAndrew Jones
Now that we pass VirtMachineState, and guest-info is just part of that state, we can remove all the redundant members and access the VirtMachineState directly. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-12-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: pass VirtMachineState instead of VirtGuestInfoAndrew Jones
Only two functions take VirtGuestInfo parameters. Now that guest-info is part of VirtMachineState, and VirtMachineState is defined in the virt header, pass that instead. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-11-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: move VirtMachineState/Class to virt.hAndrew Jones
In preparation to share more Virt machine state than just guest-info with other mach-virt source files, move the State and Class structures to virt.h Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-10-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: remove include/hw/arm/virt-acpi-build.hAndrew Jones
include/hw/arm/virt-acpi-build.h is only used for VirtGuestInfo, which doesn't even necessarily have to be ACPI specific. Move VirtGuestInfo to include/hw/arm/virt.h, allowing us to remove include/hw/arm/virt-acpi-build.h, and to prepare for even more code motion. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-9-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: eliminate struct VirtGuestInfoStateAndrew Jones
Instead of allocating a new struct just for VirtGuestInfo and the machine_done Notifier, place them inside VirtMachineState. This is the mach-virt equivalent of "pc: Eliminate struct PcGuestInfoState" Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-8-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: use VirtMachineState.gic_versionAndrew Jones
machvirt_init may need to probe for the gic version. If so, then make sure the result is written to VirtMachineState. With the state up to date, use it instead of a local variable. This is a cleanup that prepares for VirtMachineState to be passed to functions even outside hw/arm/virt.c Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-7-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: parameter passing cleanupsAndrew Jones
Some simple cleanups made possible by "hw/arm/virt: Merge VirtBoardInfo and VirtMachineState" Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20170102200153.28864-6-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: fadt: improve flag namingAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20170102200153.28864-5-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: gtdt: improve flag namingAndrew Jones
Also remove all unused flags. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20170102200153.28864-4-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriatelyAndrew Jones
Also move the enabled flag definition from mach-virt code to acpi common. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20170102200153.28864-3-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt-acpi-build: add all missing cpu_to_le'sAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20170102200153.28864-2-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggeredPeter Maydell
The architectural timers in ARM CPUs all have level triggered interrupts (unless you're using KVM on a host kernel before 4.4, which misimplemented them as edge-triggered). We were incorrectly describing them in the device tree as edge triggered. This can cause problems for guest kernels in 4.8 before rc6: * pre-4.8 kernels ignore the values in the DT * 4.8 before rc6 write the DT values to the GIC config registers * newer than rc6 ignore the DT and insist that the timer interrupts are level triggered regardless Fix the DT so we're describing reality. For backwards-compatibility purposes, only do this for the virt-2.9 machine onward. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com>
2017-01-09hw/arm/virt: Rename 'vbi' variables to 'vms'Peter Maydell
Rename all the variables which used to be VirtBoardInfo* and are now VirtMachineState* so their names are in line with the type being used. Apart from the removal of the line 'VirtMachineState *vbi = vms;' this commit is purely a search-and-replace of 'vbi' with 'vms'. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com>
2017-01-09hw/arm/virt: Merge VirtBoardInfo and VirtMachineStatePeter Maydell
One of the purposes of VirtBoardInfo was to hold various bits of state about the board. Now we have MachineState and the subclass VirtMachineState to do this. Fold the VirtBoardInfo into VirtMachineState rather than having some flags in one struct and some in another with no useful way to get between them. In the process we drop the code for looking up the memory map and irq map from the CPU model, because in practice we always use the same maps in all cases. For easier code review, this change removes the VirtBoardInfo type but leaves all the variables which used to be VirtBoardInfo* and are now VirtMachineState* with their now-confusing 'vbi' names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com>
2017-01-09hw/char: QOM'ify exynos4210_uart.cxiaoqiang zhao
Drop the old Sysbus init and use instance_init and DeviceClass::realize instead Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-09i2c: Allow I2C devices to NAK start eventsCorey Minyard
Add a return value to the event handler. Some I2C devices will NAK if they have no data, so allow them to do this. This required the following changes: Go through all the event handlers and change them to return int and return 0. Modify i2c_start_transfer to terminate the transaction on a NAK. Modify smbus handing to not assert if a NAK occurs on a second operation, and terminate the transaction and return -1 instead. Add some information on semantics to I2CSlaveClass. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-06Merge remote-tracking branch 'remotes/gonglei/tags/cryptodev-next-20161224' ↵Peter Maydell
into staging cryptodev patches - add xts mode support - add 3DES algorithm support - other trivial fixes # gpg: Signature made Sat 24 Dec 2016 05:56:44 GMT # gpg: using RSA key 0x2ED7FDE9063C864D # gpg: Good signature from "Gonglei <arei.gonglei@huawei.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3EF1 8E53 3459 E6D1 963A 3C05 2ED7 FDE9 063C 864D * remotes/gonglei/tags/cryptodev-next-20161224: cryptodev: add 3des-ede support cryptodev: remove single-DES support in cryptodev cryptodev: add xts(aes) support cryptodev: fix the check of aes algorithm Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-06Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Fri 06 Jan 2017 02:55:49 GMT # gpg: using RSA key 0xEF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: fsl_etsec: Fix Tx BD ring wrapping handling rtl8139: correctly handle PHY reset record/replay: add network support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-06fsl_etsec: Fix Tx BD ring wrapping handlingAndrey Smirnov
Current code that handles Tx buffer desciprtor ring scanning employs the following algorithm: 1. Restore current buffer descriptor pointer from TBPTRn 2. Process current descriptor 3. If current descriptor has BD_WRAP flag set set current descriptor pointer to start of the descriptor ring 4. If current descriptor points to start of the ring exit the loop, otherwise increment current descriptor pointer and go to #2 5. Store current descriptor in TBPTRn The way the code is implemented results in buffer descriptor ring being scanned starting at offset/descriptor #0. While covering 99% of the cases, this algorithm becomes problematic for a number of edge cases. Consider the following scenario: guest OS driver initializes descriptor ring to N individual descriptors and starts sending data out. Depending on the volume of traffic and probably guest OS driver implementation it is possible that an edge case where a packet, spread across 2 descriptors is placed in descriptors N - 1 and 0 in that order(it is easy to imagine similar examples involving more than 2 descriptors). What happens then is aforementioned algorithm starts at descriptor 0, sees a descriptor marked as BD_LAST, which it happily sends out as a separate packet(very much malformed at this point) then the iteration continues and the first part of the original packet is tacked to the next transmission which ends up being bogus as well. This behvaiour can be pretty reliably observed when scp'ing data from a guest OS via TAP interface for files larger than 160K (every time for 700K+). This patch changes the scanning algorithm to do the following: 1. Restore "current" buffer descriptor pointer from TBPTRn 2. If "current" descriptor does not have BD_TX_READY set, goto #6 3. Process current descriptor 4. If "current" descriptor has BD_WRAP flag set "current" descriptor pointer to start of the descriptor ring otherwise set increment "current" by the size of one descriptor 5. Goto #1 6. Save "current" buffer descriptor in TBPTRn This way we preserve the information about which descriptor was processed last and always start where we left off avoiding the original problem. On top of that, judging by the following excerpt from MPC8548ERM (p. 14-48): "... When the end of the TxBD ring is reached, eTSEC initializes TBPTRn to the value in the corresponding TBASEn. The TBPTR register is internally written by the eTSEC’s DMA controller during transmission. The pointer increments by eight (bytes) each time a descriptor is closed successfully by the eTSEC..." revised algorithm might also a more correct way of emulating this aspect of eTSEC peripheral. Cc: Alexander Graf <agraf@suse.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Jason Wang <jasowang@redhat.com> Cc: qemu-devel@nongnu.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-01-06rtl8139: correctly handle PHY resetHervé Poussineau
According to datasheet: "[Bit 15 of Basic Mode Control Register] sets the status and control registers of the PHY (register 0062-0074) in a default state. This bit is self-clearing. 1 = software reset; 0 = normal operation." This fixes the netcard detection failure in Minoca OS. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-01-06record/replay: add network supportPavel Dovgalyuk
This patch adds support of recording and replaying network packets in irount rr mode. Record and replay for network interactions is performed with the network filter. Each backend must have its own instance of the replay filter as follows: -netdev user,id=net1 -device rtl8139,netdev=net1 -object filter-replay,id=replay,netdev=net1 Replay network filter is used to record and replay network packets. While recording the virtual machine this filter puts all packets coming from the outer world into the log. In replay mode packets from the log are injected into the network device. All interactions with network backend in replay mode are disabled. v5 changes: - using iov_to_buf function instead of loop Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-01-05Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Wed 04 Jan 2017 13:29:09 GMT # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: iothread: add poll-grow and poll-shrink parameters aio: self-tune polling time virtio: disable virtqueue notifications during polling aio: add .io_poll_begin/end() callbacks virtio: turn vq->notification into a nested counter virtio-scsi: suppress virtqueue kick during processing virtio-blk: suppress virtqueue kick during processing iothread: add polling parameters linux-aio: poll ring for completions virtio: poll virtqueues for new buffers aio: add polling mode to AioContext aio: add AioPollFn and io_poll() interface aio: add flag to skip fds to aio_dispatch() HACKING: document #include order Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-05Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into stagingPeter Maydell
- transport specific callbacks (for Xen) - fix crash (2.8 regression) - 9p functional tests # gpg: Signature made Tue 03 Jan 2017 17:30:58 GMT # gpg: using DSA key 0x02FC3AEB0101DBC2 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" # gpg: aka "Greg Kurz <groug@free.fr>" # gpg: aka "Greg Kurz <gkurz@fr.ibm.com>" # gpg: aka "Greg Kurz <gkurz@linux.vnet.ibm.com>" # gpg: aka "Gregory Kurz (Groug) <groug@free.fr>" # gpg: aka "Gregory Kurz (Cimai Technology) <gkurz@cimai.com>" # gpg: aka "Gregory Kurz (Meiosys Technology) <gkurz@meiosys.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2BD4 3B44 535E C0A7 9894 DBA2 02FC 3AEB 0101 DBC2 * remotes/gkurz/tags/for-upstream: tests: virtio-9p: ".." cannot be used to walk out of the shared directory tests: virtio-9p: no slash in path elements during walk tests: virtio-9p: add walk operation test tests: virtio-9p: add attach operation test tests: virtio-9p: add version operation test 9pfs: fix P9_NOTAG and P9_NOFID macros tests: virtio-9p: code refactoring tests: virtio-9p: rename PCI configuration test 9pfs: fix crash when fsdev is missing 9pfs: introduce init_out/in_iov_from_pdu 9pfs: call v9fs_init_qiov_from_pdu before v9fs_pack 9pfs: introduce transport specific callbacks 9pfs: move pdus to V9fsState Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-05Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20170103-1' into ↵Peter Maydell
staging virtio-gpu: misc bugfixes. # gpg: Signature made Tue 03 Jan 2017 14:48:04 GMT # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/pull-vga-20170103-1: virtio-gpu: fix memory leak in resource attach backing virtio-gpu-3d: fix memory leak in resource attach backing virtio-gpu: call cleanup mapping function in resource destroy virtio-gpu: track and limit host memory allocations display: virtio-gpu-3d: check virgl capabilities max_size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-03iothread: add poll-grow and poll-shrink parametersStefan Hajnoczi
These parameters control the poll time self-tuning algorithm. They are optional and will default to sane values if omitted. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20161201192652.9509-14-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-03aio: self-tune polling timeStefan Hajnoczi
This patch is based on the algorithm for the kvm.ko halt_poll_ns parameter in Linux. The initial polling time is zero. If the event loop is woken up within the maximum polling time it means polling could be effective, so grow polling time. If the event loop is woken up beyond the maximum polling time it means polling is not effective, so shrink polling time. If the event loop makes progress within the current polling time then the sweet spot has been reached. This algorithm adjusts the polling time so it can adapt to variations in workloads. The goal is to reach the sweet spot while also recognizing when polling would hurt more than help. Two new trace events, poll_grow and poll_shrink, are added for observing polling time adjustment. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20161201192652.9509-13-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>