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2012-04-20target-arm: Move A9 config_base_address reset value to ARMCPUdrop-reset-model-idPeter Maydell
Move the A9 config_base_address cp15 register reset value to ARMCPU. This should become a QOM property so that the Highbank board can set it without having to pull in cpu-qom.h, but at least this avoids the implicit dependency on reset ordering that the previous workaround had. Cc: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-20target-arm: Move reset handling to arm_cpu_resetPeter Maydell
Now that cpu_reset_model_id() has gone we can move the reset code over to the class reset function and have cpu_state_reset simply do a reset on the CPU QOM object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Drop cpu_reset_model_id()Peter Maydell
cpu_reset_model_id() is now empty and we can remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Move cache ID register setup to cpu specific init fnsPeter Maydell
Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_resetPeter Maydell
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Move feature register setup to per-CPU init fnsPeter Maydell
Move feature register value setup to per-CPU init functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Move iWMMXT wCID reset to cpu_state_resetPeter Maydell
Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Drop JTAG_ID documentationPeter Maydell
None of the machines in QEMU offer a JTAG debug interface, so this info was unused. Further, the PXA250 ID contradicts the February 2002 Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-20target-arm: Move SCTLR reset value setup to per cpu init fnsPeter Maydell
Move the reset value of SCTLR to ARMCPU, initialised in the per-cpu init functions. It can then be reset by a simple copy, and we can drop the code from cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Move CTR setup to per cpu init fnsPeter Maydell
Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Move MVFR* setup to per cpu init fnsPeter Maydell
Move the MVFR* VFP feature register values to ARMCPU, so they are set up by the implementation-specific instance init functions rather than in cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-20target-arm: Move FPSID config to cpu init fnsPeter Maydell
Move the reset FPSID to the ARMCPU struct, and set it in the per-implementation instance init function. At reset we then just copy the reset value into the CPUARMState field. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-17target-arm: Move feature bit settings to CPU init fnsPeter Maydell
Move the setting of the feature bits from cpu_reset_model_id() to each CPU's instance init function. This requires us to move the features field in CPUARMState so that it is not cleared on reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-14target-arm: Add QOM subclasses for each ARM cpu implementationPeter Maydell
Register subclasses for each ARM CPU implementation. Let arm_cpu_list() enumerate CPU subclasses in alphabetical order, except for special value "any". Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the CPUID (aka MIDR, Main ID Register) value in the class. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-14Use uintptr_t for various op related functionsBlue Swirl
Use uintptr_t instead of void * or unsigned long in several op related functions, env->mem_io_pc and GETPC() macro. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14coroutine-gthread.c: Avoid threading APIs deprecated in GLib 2.31Peter Maydell
The GLib threading APIs were revamped in GLib 2.31 and a number of the old interfaces were deprecated, which means they provoke compilation warnings (errors if -Werror) now. Add support for the new interfaces while retaining the old ones so we can still compile on older versions of GLib too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14Merge branch 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensaBlue Swirl
* 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa: target-xtensa: Start QOM'ifying CPU init target-xtensa: QOM'ify CPU reset target-xtensa: QOM'ify CPU target-xtensa: improve unit tests debugging target-xtensa: Move helpers.h to helper.h
2012-04-14Merge branch 'arm-devs.for-upstream' of ↵Blue Swirl
git://git.linaro.org/people/pmaydell/qemu-arm * 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: hw/arm_gic: Remove stray hardcoded tab hw/arm_gic: gic_set_pending_private() is NVIC only hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC define hw/arm_gic: Make gic_reset a sysbus reset function hw/arm11mpcore: Convert to using sysbus GIC device hw/exynos4210_gic: Convert to using sysbus GIC hw/realview_gic: switch to sysbus GIC hw/a9mpcore: Switch to using sysbus GIC hw/a15mpcore: switch to using sysbus GIC hw/arm_gic: Make the GIC its own sysbus device hw/arm_gic: Expose PPI inputs as gpio inputs hw/arm_gic: Move gic_get_current_cpu into arm_gic.c hw/arm_gic: Move NCPU definition to arm_gic.c hw/exynos4210_combiner.c: Drop excessive read/write access check. ARM: Exynos4210: Drop gic_cpu_write() after initialization. Fix bit test in Exynos4210 UART emulation to use & instead of &&
2012-04-14target-xtensa: Start QOM'ifying CPU initAndreas Färber
Move XtensaConfig-independent code from cpu_xtensa_init() into a QOM initfn, as a start. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber
Move code from cpu_state_reset() into QOM xtensa_cpu_reset(). To avoid moving reset_mmu() and dependencies, make it non-static. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber
Embed CPUXtensaState as first member of XtensaCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: improve unit tests debuggingMax Filippov
- add testcase announcement; - add global symbols for individual tests; - add host-debug-* makefile target. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova
Provides a file naming scheme consistent with other targets. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-13Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori
* stefanha/trivial-patches: configure: Insist on a Python 2, not Python 3 bsd-user: fix compile failure ps2: avoid repeated header file includes make: Always set LC_ALL=C for makeinfo configure: Fix wrong preprocessor statement configure: Remove useless uses of ARCH_CFLAGS
2012-04-13Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori
* qemu-kvm/uq/master: kvmclock: guest stop notification kvm: update linux headers kvm: set gsi_bits and max_gsi correctly kvm: Drop unused kvm_pit_in_kernel kvm: allow arbitrarily sized mmio ioeventfd kvm: Drop redundant kvm_enabled from cpu_thread_is_idle kvm: add flightrecorder script
2012-04-13Merge remote-tracking branch 'afaerber/qom-cpu-lm32.v3' into stagingAnthony Liguori
* afaerber/qom-cpu-lm32.v3: target-lm32: QOM'ify CPU reset target-lm32: QOM'ify CPU init target-lm32: QOM'ify CPU
2012-04-13hw/arm_gic: Remove stray hardcoded tabPeter Maydell
Remove the single instance of a hardcoded tab from hw/arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: gic_set_pending_private() is NVIC onlyPeter Maydell
The function gic_set_pending_private() is now used by the NVIC only (for the GIC we now set PPI interrupts via gpio lines and gic_set_irq()). So make it #ifdef NVIC and remove the 'attribute unused' annotation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC definePeter Maydell
Now all the A profile cores have been switched to use the standalone sysbus GIC, the only remaining code which #includes arm_gic.c is the v7M NVIC. The coupling is much closer here so it's not so easily disentangled. For now, add a comment about how arm_gic.c is compiled, and assume that the NVIC always includes arm_gic.c and the non-NVIC GIC is always compiled standalone. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make gic_reset a sysbus reset functionPeter Maydell
Make gic_reset a sysbus reset function, so we actually reset the GIC on system reset rather than only at init. For the NVIC this requires us also to implement reset of the SysTick. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm11mpcore: Convert to using sysbus GIC devicePeter Maydell
Convert arm11mpcore to using the standalone sysbus GIC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/exynos4210_gic: Convert to using sysbus GICPeter Maydell
Convert the Exynos GIC code to use the standalone sysbus GIC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/realview_gic: switch to sysbus GICPeter Maydell
Switch the realview_gic device to the standalone sysbus GIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/a9mpcore: Switch to using sysbus GICPeter Maydell
Switch the a9mpcore to using the sysbus GIC device rather than having the a9mp private memory region device subclass the GIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/a15mpcore: switch to using sysbus GICPeter Maydell
Switch the a15mpcore private peripheral region to using the standalone sysbus GIC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make the GIC its own sysbus devicePeter Maydell
Compile arm_gic.c as a standalone C file to produce a self contained sysbus GIC device. Support the legacy usage by #include of the .c file by making those users #define LEGACY_INCLUDED_GIC, so we can convert them one by one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Expose PPI inputs as gpio inputsPeter Maydell
Expose the Private Peripheral Interrupt inputs as GPIO inputs. The layout of the GPIO array is thus: [0..N-1] SPIs [N..N+31] PPIs for CPU 0 [N+32..N+63] PPIs for CPU 1 ... Treating PPIs as being another kind of input line is in line with the GIC architecture specification, where they are clearly described that way. The 11MPCore TRM is a bit more ambiguous, but there is no practical difference between "set PPI X as pending" and "0->1 transition on a PPI input line configured as edge triggered", and PPIs are always edge triggered, so this change won't affect behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Move gic_get_current_cpu into arm_gic.cPeter Maydell
Move the gic_get_current_cpu() function into arm_gic.c. There are only two implementations: (1) "get the index of the currently executing CPU", used by all multicore GICs, and (2) "always 0", used by all GICs instantiated with a single CPU interface (the Realview board GIC and the v7M NVIC). So we can move this into the main GIC source file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Move NCPU definition to arm_gic.cPeter Maydell
Move the NCPU definition to arm_gic.c: the maximum number of CPU interfaces is defined by the GIC architecture specification to be 8, so we don't need to have this #define in each of the sources files which currently includes arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/exynos4210_combiner.c: Drop excessive read/write access check.Evgeny Voevodin
Access to reserved area at offset higher than 0x3c is allowed in External Combiner. Samsung Galaxy Kernel implements this. So, drop excessive checks in read/write functions. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13ARM: Exynos4210: Drop gic_cpu_write() after initialization.Evgeny Voevodin
Remove gic_cpu_write() call after initialization that was emulating functionality of earliest SOC bootloader which enables external GIC CPU1 interface. Instead introduce Exynos4210-specific secondary CPU bootloader, which enables both Internal and External GIC CPU1 interfaces. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13Fix bit test in Exynos4210 UART emulation to use & instead of &&Daniel P. Berrange
* hw/exynos4210_uart.c: s/&&/&/ Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13configure: Insist on a Python 2, not Python 3Peter Maydell
Our Python scripts require Python 2 and will fail on Python 3, eg: File "/home/petmay01/linaro/qemu-from-laptop/qemu/scripts/qapi-commands.py", line 378 except getopt.GetoptError, err: ^ SyntaxError: invalid syntax Add a check to configure that Python is not a Python 3, so we can fail with a comprehensible error rather than an obscure one. Reported-by: Boris Matti <swiftos@lavabit.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-04-13bsd-user: fix compile failurePeter Maydell
bsd-user doesn't actually support reserving a memory area for the guest address space, but we need to at least define the reserved_va global so that cpu-all.h's RESERVED_VA macro will work correctly. This fixes a compilation error introduced in commit 39879bb which added a use of RESERVED_VA to h2g_valid(). Reported-by: Brad Smith <brad@comstyle.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-04-12kvmclock: guest stop notificationEric B Munson
Often when a guest is stopped from the qemu console, it will report spurious soft lockup warnings on resume. There are kernel patches being discussed that will give the host the ability to tell the guest that it is being stopped and should ignore the soft lockup warning that generates. This patch uses the qemu Notifier system to tell the guest it is about to be stopped. Signed-off-by: Eric B Munson <emunson@mgebm.net> Signed-off-by: Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-04-12kvm: update linux headersMarcelo Tosatti
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-04-12kvm: set gsi_bits and max_gsi correctlyJason Baron
The current kvm_init_irq_routing() doesn't set up the used_gsi_bitmap correctly, and as a consequence pins max_gsi to 32 when it really should be 1024. I ran into this limitation while testing pci passthrough, where I consistently got an -ENOSPC return from kvm_get_irq_route_gsi() called from assigned_dev_update_msix_mmio(). Signed-off-by: Jason Baron <jbaron@redhat.com> Acked-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-04-12kvm: Drop unused kvm_pit_in_kernelJan Kiszka
This is now implied by kvm_irqchip_in_kernel. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-04-12kvm: allow arbitrarily sized mmio ioeventfdMichael S. Tsirkin
We use a 2 byte ioeventfd for virtio memory, add support for this. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Amos Kong <akong@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2012-04-12kvm: Drop redundant kvm_enabled from cpu_thread_is_idleJan Kiszka
This is now implied by kvm_irqchip_in_kernel. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>