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2014-08-19target-arm: Implement MDSCR_EL1 as having statedebugPeter Maydell
Now that all the new code to support single-stepping is in place, wire up the guest-visible MDSCR_EL1, so the guest can enable single-stepping. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell
ARMv8 single-stepping requires the exception level that controls the single-stepping to be in AArch64 execution state, but the code being stepped may be in AArch64 or AArch32. Implement the necessary support code for single-stepping AArch32 code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell
Implement ARMv8 software single-step handling for A64 code: correctly update the single-step state machine and generate debug exceptions when stepping A64 code. This patch has no behavioural change since MDSCR_EL1.SS can't be set by the guest yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell
If gen_goto_tb() decides not to link the two TBs, then the fallback path generates unnecessary code: * if singlestep is enabled then we generate unreachable code after the gen_exception_internal(EXCP_DEBUG) * if singlestep is disabled then we will generate exit_tb(0) twice, once in gen_goto_tb() and once coming out of the main loop with is_jmp set to DISAS_JUMP Correct these deficiencies by only emitting exit_tb() in the non-singlestep case, in which case we can use DISAS_TB_JUMP to suppress the main-loop exit_tb(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell
Set the PSTATE.SS bit correctly on exception returns from AArch64, as required by the debug single-step functionality. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell
When an exception is taken to AArch32, we must clear the PSTATE.SS bit for the exception handler, and must also ensure that the SS bit is not set in the value saved to SPSR_<mode>. Achieve both of these aims by clearing the bit in uncached_cpsr before saving it to the SPSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell
The CPSR has a new-in-v8 execution state bit (IL), and also some state which has effects in AArch32 but appears only in the SPSR format (SS) but is RES0 in the CPSR. Add the IL bit to CPSR_EXEC, and enforce that guest direct reads and writes to CPSR can't read or write the RES0 bits, so the guest can't get at the SS bit which we store in uncached_cpsr. This includes not permitting exception returns to copy reserved bits from an SPSR into CPSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Adjust debug ID registers per-CPUPeter Maydell
Allow each CPU type to specify the value for the debug ID registers, by putting them in the ARMCPU struct, and use the resulting information to only expose the correct number of watchpoint and breakpoint registers for the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell
Bring the 32 bit and 64 bit views of the debug registers into line by providing the same set of registers in both cases. (This still isn't a complete set, but it is consistent.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell
Currently the STATE_BOTH shorthand for allowing a single reginfo struct to define handling for both AArch32 and AArch64 views of a register only permits this where the AArch32 view is in cp15. It turns out that the debug registers in cp14 also have neatly lined up encodings; allow these also to share reginfo structs by permitting a STATE_BOTH reginfo to specify the .cp field (and continue to default to 15 if it is not specified). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Collect up the debug cp register definitionsPeter Maydell
At the moment we have a mixed set of mostly dummy register definitions for various debug related registers which have been added piecemeal in order to get Linux kernels to boot. In preparation for actually implementing debug support, bring them all together into one place. This commit doesn't change behaviour: we still expose exactly the same registers and behaviour to the guest in all configurations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-18target-arm: Fix return address for A64 BRK instructionsPeter Maydell
When we take an exception resulting from a BRK instruction, the architecture requires that the "preferred return address" reported to the exception handler is the address of the BRK itself, not the following instruction (like undefined insns, and in contrast with SVC, HVC and SMC). Follow this, rather than incorrectly reporting the address of the following insn. (We do get this correct for the A32/T32 BKPT insns.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-07Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
KVM changes include a MIPS patch and the testdev backend used by the ARM kvm-unit-tests. icount include the first part of reverse execution and Sebastian Tanase's patches to slow down -icount execution to the desired speed of the target. v1->v2: fix dump_drift_info to print nothing outside icount mode, and to compile on 32-bit architectures # gpg: Signature made Thu 07 Aug 2014 14:09:58 BST using RSA key ID 9B4D86F2 # gpg: Good signature from "Paolo Bonzini <pbonzini@redhat.com>" # gpg: aka "Paolo Bonzini <bonzini@gnu.org>" * remotes/bonzini/tags/for-upstream: target-mips: Ignore unassigned accesses with KVM monitor: Add drift info to 'info jit' cpu-exec: Print to console if the guest is late cpu-exec: Add sleeping algorithm icount: Add align option to icount icount: Add QemuOpts for icount icount: Fix virtual clock start value on ARM timer: add cpu_icount_to_ns function. migration: migrate icount fields. icount: put icount variables into TimerState. backends: Introduce chr-testdev Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-07target-mips: Ignore unassigned accesses with KVMJames Hogan
MIPS registers an unassigned access handler which raises a guest bus error exception. However this causes QEMU to crash when KVM is enabled as it isn't called from the main execution loop so longjmp() gets called without a corresponding setjmp(). Until the KVM API can be updated to trigger a guest exception in response to an MMIO exit, prevent the bus error exception being raised from mips_cpu_unassigned_access() if KVM is enabled. The check is at run time since the do_unassigned_access callback is initialised before it is known whether KVM will be enabled. The problem can be triggered with Malta emulation by making the guest write to the reset region at physical address 0x1bf00000, since it is marked read-only which is treated as unassigned for writes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-07monitor: Add drift info to 'info jit'Sebastian Tanase
Show in 'info jit' the current delay between the host clock and the guest clock. In addition, print the maximum advance and delay of the guest compared to the host. Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-07Merge remote-tracking branch ↵Peter Maydell
'remotes/awilliam/tags/vfio-pci-for-qemu-20140805.0' into staging VFIO patches: Fix MSI-X vector expansion, remove MSI/X message caching # gpg: Signature made Tue 05 Aug 2014 20:25:57 BST using RSA key ID 3BB08B22 # gpg: Can't check signature: public key not found * remotes/awilliam/tags/vfio-pci-for-qemu-20140805.0: vfio: Don't cache MSIMessage vfio: Fix MSI-X vector expansion Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-06cpu-exec: Print to console if the guest is lateSebastian Tanase
If the align option is enabled, we print to the user whenever the guest clock is behind the host clock in order for he/she to have a hint about the actual performance. The maximum print interval is 2s and we limit the number of messages to 100. If desired, this can be changed in cpu-exec.c Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06cpu-exec: Add sleeping algorithmSebastian Tanase
The goal is to sleep qemu whenever the guest clock is in advance compared to the host clock (we use the monotonic clocks). The amount of time to sleep is calculated in the execution loop in cpu_exec. At first, we tried to approximate at each for loop the real time elapsed while searching for a TB (generating or retrieving from cache) and executing it. We would then approximate the virtual time corresponding to the number of virtual instructions executed. The difference between these 2 values would allow us to know if the guest is in advance or delayed. However, the function used for measuring the real time (qemu_clock_get_ns(QEMU_CLOCK_REALTIME)) proved to be very expensive. We had an added overhead of 13% of the total run time. Therefore, we modified the algorithm and only take into account the difference between the 2 clocks at the begining of the cpu_exec function. During the for loop we try to reduce the advance of the guest only by computing the virtual time elapsed and sleeping if necessary. The overhead is thus reduced to 3%. Even though this method still has a noticeable overhead, it no longer is a bottleneck in trying to achieve a better guest frequency for which the guest clock is faster than the host one. As for the the alignement of the 2 clocks, with the first algorithm the guest clock was oscillating between -1 and 1ms compared to the host clock. Using the second algorithm we notice that the guest is 5ms behind the host, which is still acceptable for our use case. The tests where conducted using fio and stress. The host machine in an i5 CPU at 3.10GHz running Debian Jessie (kernel 3.12). The guest machine is an arm versatile-pb built with buildroot. Currently, on our test machine, the lowest icount we can achieve that is suitable for aligning the 2 clocks is 6. However, we observe that the IO tests (using fio) are slower than the cpu tests (using stress). Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06icount: Add align option to icountSebastian Tanase
The align option is used for activating the align algorithm in order to synchronise the host clock and the guest clock. Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06icount: Add QemuOpts for icountSebastian Tanase
Make icount parameter use QemuOpts style options in order to easily add other suboptions. Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06icount: Fix virtual clock start value on ARMSebastian Tanase
When using the icount option on ARM, the virtual clock starts counting at realtime clock but it should start at 0. The reason why the virtual clock starts at realtime clock is because the first time we call qemu_clock_warp (which calls icount_warp_rt) in tcg_exec_all, qemu_icount_bias (which is part of the virtual time computation mechanism) will increment by realtime - vm_clock_warp_start, with vm_clock_warp_start being 0 (see icount_warp_rt in cpus.c). By changing the value of vm_clock_warp_start from 0 to -1, the first time we call qemu_clock_warp which calls icount_warp_rt, we will return immediatly because icount_warp_rt first checks if vm_clock_warp_start is -1 and if it's the case it returns. Therefore, qemu_icount_bias will first be incremented by the value of a virtual timer deadline when the virtual cpu goes from active to inactive. The virtual time will start at 0 and increment based on the instruction counter when the vcpu is active or the qemu_icount_bias value when inactive. Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06timer: add cpu_icount_to_ns function.KONRAD Frederic
This adds cpu_icount_to_ns function which is needed for reverse execution. It returns the time for a specific instruction. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06migration: migrate icount fields.KONRAD Frederic
This fixes a bug where qemu_icount and qemu_icount_bias are not migrated. It adds a subsection "timer/icount" to vmstate_timers so icount is migrated only when needed. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06icount: put icount variables into TimerState.KONRAD Frederic
This puts qemu_icount and qemu_icount_bias into TimerState structure to allow them to be migrated. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06backends: Introduce chr-testdevPaolo Bonzini
From: Paolo Bonzini <pbonzini@redhat.com> chr-testdev enables a virtio serial channel to be used for guest initiated qemu exits. hw/misc/debugexit already enables guest initiated qemu exits, but only for PC targets. chr-testdev supports any virtio-capable target. kvm-unit-tests/arm is already making use of this backend. Currently there is a single command implemented, "q". It takes a (prefix) argument for the exit code, thus an exit is implemented by writing, e.g. "1q", to the virtio-serial port. It can be used as: $QEMU ... \ -device virtio-serial-device \ -device virtserialport,chardev=ctd -chardev testdev,id=ctd or, use: $QEMU ... \ -device virtio-serial-device \ -device virtconsole,chardev=ctd -chardev testdev,id=ctd to bind it to virtio-serial port0. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-05vfio: Don't cache MSIMessageAlex Williamson
Commit 40509f7f added a test to avoid updating KVM MSI routes when the MSIMessage is unchanged and f4d45d47 switched to relying on this rather than doing our own comparison. Our cached msg is effectively unused now. Remove it. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2014-08-05vfio: Fix MSI-X vector expansionAlex Williamson
When new MSI-X vectors are enabled we need to disable MSI-X and re-enable it with the correct number of vectors. That means we need to reprogram the eventfd triggers for each vector. Prior to f4d45d47 vector->use tracked whether a vector was masked or unmasked and we could always pick the KVM path when available for unmasked vectors. Now vfio doesn't track mask state itself and vector->use and virq remains configured even for masked vectors. Therefore we need to ask the MSI-X code whether a vector is masked in order to select the correct signaling path. As noted in the comment, MSI relies on hardware to handle masking. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Cc: qemu-stable@nongnu.org # QEMU 2.1
2014-08-04Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20140804' into staging target-arm queue: * Set PC correctly when loading AArch64 ELF files * sdhci: Fix ADMA dma_memory_read access * some more foundational work for EL2/EL3 support * fix bugs which reveal themselves if the TARGET_PAGE_SIZE is not set to 1K # gpg: Signature made Mon 04 Aug 2014 14:51:34 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140804: target-arm: A64: fix TLB flush instructions target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault target-arm: Fix bit test in sp_el0_access target-arm: Add FAR_EL2 and 3 target-arm: Add ESR_EL2 and 3 target-arm: Make far_el1 an array target-arm: A64: Respect SPSEL when taking exceptions target-arm: A64: Respect SPSEL in ERET SP restore target-arm: A64: Break out aarch64_save/restore_sp sd: sdhci: Fix ADMA dma_memory_read access hw/arm/virt: formatting: memory map hw/arm/boot: Set PC correctly when loading AArch64 ELF files Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: A64: fix TLB flush instructionspull-target-arm-20140804Alex Bennée
According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée
Otherwise we break quickly when we change TARGET_PAGE_SIZE. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1406733627-24255-2-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Fix bit test in sp_el0_accessStefan Weil
Static code analyzers complain about a dubious & operation used for a boolean value. The code does not test the PSTATE_SP bit as it should. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1406359601-25583-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias
No functional change. Prepares for future additions of the EL2 and 3 versions of this reg. Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1402994746-8328-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: A64: Respect SPSEL in ERET SP restoreEdgar E. Iglesias
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1402994746-8328-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: A64: Break out aarch64_save/restore_spEdgar E. Iglesias
Break out code to save/restore AArch64 SP into functions. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1402994746-8328-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04sd: sdhci: Fix ADMA dma_memory_read accessPeter Crosthwaite
This dma_memory_read was giving too big a size when begin was non-zero. This could cause segfaults in some circumstances. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04hw/arm/virt: formatting: memory mapAndrew Jones
Add some spacing and zeros to make it easier to read and modify the map. This patch has no functional changes. The review looks ugly, but it's actually pretty easy to confirm all the addresses are as they should be - thanks to the new formatting ;-) Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04hw/arm/boot: Set PC correctly when loading AArch64 ELF filesPeter Maydell
The code in do_cpu_reset() correctly handled AArch64 CPUs when running Linux kernels, but was missing code in the branch of the if() that deals with loading ELF files. Correctly jump to the ELF entry point on reset rather than leaving the reset PC at zero. Reported-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Christopher Covington <cov@codeaurora.org> Cc: qemu-stable@nongnu.org
2014-08-04Merge remote-tracking branch 'remotes/amit-migration/for-2.2' into stagingPeter Maydell
* remotes/amit-migration/for-2.2: checker: ignore fields marked unused vmstate static checker: whitelist additions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04Merge remote-tracking branch 'remotes/amit-virtio-rng/for-2.2' into stagingPeter Maydell
* remotes/amit-virtio-rng/for-2.2: virtio-rng: replace error_set calls with error_setg virtio-rng: Move error-checking forward to prevent memory leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04Merge remote-tracking branch 'remotes/sstabellini/xen-20140801' into stagingPeter Maydell
* remotes/sstabellini/xen-20140801: qemu: support xen hvm direct kernel boot tap-bsd: implement a FreeBSD only version of tap_open xen: fix usage of ENODATA Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04checker: ignore fields marked unusedAmit Shah
While comparing qemu-1.0 json output with qemu-2.1, a few fields got marked unused. These need to be skipped over, and not flagged as mismatches. For handling unused fields, the exact number of bytes need to be skipped over as the size of the unused field. Currently, only the term "unused" is matched. When more field names turn up, this will have to be updated based on the whitelist matching method to match more such terms. Signed-off-by: Amit Shah <amit.shah@redhat.com>
2014-08-04virtio-rng: replace error_set calls with error_setgJohn Snow
Under recommendation from Luiz Capitulino, we are changing the error_set calls to error_setg while we are fixing up the error handling pathways of virtio-rng. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2014-08-04virtio-rng: Move error-checking forward to prevent memory leakJohn Snow
This patch pushes the error-checking forward and the virtio initialization backward in the device realization function in order to prevent memory leaks for hot plug scenarios. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2014-08-01Open 2.2 development treePeter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-01qemu: support xen hvm direct kernel bootChunyan Liu
qemu side patch to support xen HVM direct kernel boot: if -kernel exists, calls xen_load_linux(), which will read kernel/initrd and add a linuxboot.bin or multiboot.bin option rom. The linuxboot.bin/multiboot.bin will load kernel/initrd and jump to execute kernel directly. It's working when xen uses seabios. During this work, found the 'kvmvapic' is in option_rom list, it should not be there in xen case. Set s->vapic_control = 0 in xen_apic_realize() to handle that. Signed-off-by: Chunyan Liu <cyliu@suse.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
2014-08-01tap-bsd: implement a FreeBSD only version of tap_openRoger Pau Monne
The current behaviour of tap_open for BSD systems differ greatly from it's Linux counterpart. Since FreeBSD supports interface renaming and tap device cloning by opening /dev/tap, implement a FreeBSD specific version of tap_open that behaves like it's Linux counterpart. This is specially important for toolstacks that use Qemu (like Xen libxl), in order to have a unified behaviour across suported platforms. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-08-01xen: fix usage of ENODATARoger Pau Monne
ENODATA doesn't exist on FreeBSD, so ENODATA errors returned by the hypervisor are translated to ENOENT. Also, the error code is returned in errno if the call returns -1, so compare the error code with the value in errno instead of the value returned by the function. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Cc: xen-devel@lists.xenproject.org Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Cc: Anthony Perard <anthony.perard@citrix.com>