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2012-07-16hw/vexpress.c: Allow >4GB of RAM for Cortex-A15 daughterboardboot-fix-int-sizesPeter Maydell
Now that we have LPAE support and can handle passing 64 bit RAM sizes to Linux via the device tree, we can lift the restriction in the Versatile Express A15 daughterboard model on not having more than 2GB of RAM. Allow up to 30GB, which is the maximum that can fit in the address map before running into the (unmodelled) aliases of the first 2GB. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-16hw/arm_boot.c: Support DTBs which use 64 bit addressesPeter Maydell
Support the case where the device tree blob specifies that #address-cells and #size-cells are greater than 1. (This is needed for device trees which can handle 64 bit physical addresses and thus total RAM sizes over 4GB.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-07-16device_tree: Add support for reading device tree propertiesPeter Maydell
Add support for reading device tree properties (both generic and single-cell ones) to QEMU's convenience wrapper layer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-16hw/arm_boot.c: Check for RAM sizes exceeding ATAGS capacityPeter Maydell
The legacy ATAGS format for passing information to the kernel only allows RAM sizes which fit in 32 bits; enforce this restriction rather than silently doing something weird. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-16hw/arm_boot.c: Consistently use ram_size from arm_boot_info structPeter Maydell
Clean up the mix of getting the RAM size from the global ram_size and from the ram_size field in the arm_boot_info structure, so that we always use the structure field. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-07-16hw/arm_boot.c: Make ram_size a uint64_tPeter Maydell
Make the RAM size in arm_boot_info a uint64_t so it can express the larger RAM sizes that may be seen in LPAE systems. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-14qemu-log: fix x86 and user loggingBlue Swirl
5726c27fa913296aafab9f50b912cea5b3709271 broke x86 specific options and user emulation specific stdio buffering. Always enable all log items. They may not be useful for non-x86 targets, but there's no harm either. Fix user emulation buffering by passing around a flag. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14Merge branch 'trivial-patches' of git://github.com/stefanha/qemuBlue Swirl
* 'trivial-patches' of git://github.com/stefanha/qemu: make: Remove 'build-all' rule qemu-keymaps: Finnish keyboard mapping broken vnc: add a more descriptive error message bitops: Fix documentation megasas: mark mfi_frame_desc as 'static'
2012-07-14vga: Implement blinking of text cursorJan Kiszka
Let the text cursor blink at 1.875 Hz, the original VGA cursor frequency. No timer is used, instead we rely on the fact that the display is updated periodically. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14console: Implementing blinking of cursorJan Kiszka
Let the text console cursor blink at 2 HZ. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14configure: add -Werror to QEMU_CFLAGS earlyAlexander Graf
We want all configure tests pass with -Werror if it is enabled. So we need to update QEMU_CFLAGS early on to make sure we also pass it in to all the compile test jobs. This fixes a warning-became-error bug in nss for me with the default configuration: In file included from /usr/include/nss3/pkcs11t.h:1780, from /usr/include/nss3/keythi.h:41, from /usr/include/nss3/keyt.h:41, from /usr/include/nss3/pk11pub.h:43, from libcacard/vcard_emul_nss.c:21: /usr/include/nss3/pkcs11n.h:365:26: error: "__GNUC_MINOR" is not defined Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14monitor: Use TARGET_PRI*PHYS to avoid TARGET_PHYS_ADDR_BITS ifdefPeter Maydell
Now we have TARGET_PRI*PHYS for printing target_phys_addr_t values, we can use them in monitor.c rather than having duplicate code in two arms of a TARGET_PHYS_ADDR_BITS ifdef. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14hw/sh_serial: Use TARGET_PRIxPHYS rather than %x for physaddrPeter Maydell
Switch a format string from %x to TARGET_PRIxPHYS so that it will continue to work even if target_phys_addr_t is changed to 64 bits in the future. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14hw/omap.h: Use TARGET_PRIxPHYS to define OMAP_FMT_plxPeter Maydell
Use the new TARGET_PRIxPHYS macro to avoid the need to define an OMAP_FMT_plx macro whose expansion depends directly on TARGET_PHYS_ADDR_BITS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14targphys.h: Define TARGET_PRI*PHYS format specifier macrosPeter Maydell
Define a set of TARGET_PRI*PHYS format specifier macros for working with target_phys_addr_t types. These follow the standard pattern for such macros, and are more flexible than TARGET_FMT_plx, which does not allow specification of field widths. Suggested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14disas: Fix printing of addresses in disassemblyPeter Maydell
In our disassembly code, the bfd_vma type is always 64 bits, even if the target's virtual address width is only 32 bits. This means that when we print out addresses we need to truncate them to 32 bits, to avoid odd output which has incorrectly sign-extended a value to 64 bits, for instance this ARM example: 0x80479a60: e59f4088 ldr r4, [pc, #136] ; 0xffffffff80479a4f (It would also be possible to truncate before passing the address to info->print_address_func(), but truncating in the final print function is the same approach that binutils takes to this problem.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: add AMD PCscsi emulation (PCI SCSI adapter)Hervé Poussineau
The PCI version is supported in lots of Operating Systems, and has been successfully tested on: - MS DOS 6.22 (using DC390 driver) - MS Windows 3.11 (using DC390 driver) - MS Windows 98 SE (using default driver) - MS Windows NT 3.1 (using DC390 driver) - MS Windows NT 4.0 (using default driver) Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14pci: add some stubsHervé Poussineau
Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: use trace framework instead of stderr outputHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: split esp code into generic chip emulation and sysbus layerHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: use hba_private field instead of a complex castHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: support future change of chip_idHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: implement Reset ATN commandHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: implement Disable selection commandHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: delay Transfer Information command if dma is not enabledHervé Poussineau
The same mechanism is already in place for some select commands. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14esp: execute select commands immediately when it is a non-dma commandHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-14Merge branch 's390-for-upstream' of git://repo.or.cz/qemu/agrafBlue Swirl
* 's390-for-upstream' of git://repo.or.cz/qemu/agraf: s390: autodetect map private
2012-07-14Merge branch 'target-arm.for-upstream' of ↵Blue Swirl
git://git.linaro.org/people/pmaydell/qemu-arm * 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: target-arm: Add support for long format translation table walks target-arm: Implement TTBCR changes for LPAE target-arm: Implement long-descriptor PAR format target-arm: Use target_phys_addr_t in get_phys_addr() target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers target-arm: Extend feature flags to 64 bits target-arm: Implement privileged-execute-never (PXN) ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits target-arm: Fix TCG temp handling in 64 bit cp writes target-arm: Fix some copy-and-paste errors in cp register names target-arm: Fix typo that meant TTBR1 accesses went to TTBR0 target-arm: Fix CP15 based WFI
2012-07-13make: Remove 'build-all' ruleStefan Weil
It is not needed, because the 'all' rule does the same. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-07-13qemu-keymaps: Finnish keyboard mapping brokenMichael Tokarev
As mentioned in http://bugs.debian.org/660154 , finnish keyboard mapping is kind of broken. Fix it as Timo Sirainen suggests in #660154. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-07-13vnc: add a more descriptive error messageAmos Kong
Currently qemu outputs some low-level error in qemu-sockets.c when failed to start vnc server. eg. 'getaddrinfo(127.0.0.1,5902): Name or service not known' Some libvirt users could not know what's happened with this unclear error message. This patch added a more descriptive error message. Signed-off-by: Amos Kong <akong@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-07-13bitops: Fix documentationStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-07-13megasas: mark mfi_frame_desc as 'static'Hannes Reinecke
Suggested by blue swirl. Patch is on top of Paolo's scsi-next tree. Signed-off-by: Hannes Reinecke <hare@suse.de> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-07-12target-arm: Add support for long format translation table walksPeter Maydell
Implement the actual table walk code for LPAE's long format translation tables. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Implement TTBCR changes for LPAEPeter Maydell
Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Implement long-descriptor PAR formatPeter Maydell
Implement the different format of the PAR when long descriptor translation tables are in use. Note that we assume that get_phys_addr() returns a long-descriptor format DFSR value on failure if long descriptors are in use; this added subtlety tips the balance and makes it worth adding a comment documenting the API to get_phys_addr(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Use target_phys_addr_t in get_phys_addr()Peter Maydell
In the implementation of get_phys_addr(), consistently use target_phys_addr_t to hold the physical address rather than uint32_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the full width of the register. Add the state fields for the top half and the 64 bit access path. Actual use of the top half of the register will come with the addition of the long-descriptor translation table format support. For the PAR we also need to correct the masking applied for 32 bit writes (there are no bits reserved if LPAE is implemented) and clear the high half when doing a 32 bit result VA-to-PA lookup. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAEPeter Maydell
LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; we only implement these as dummy RAZ versions; provide dummies for the 64 bit accesses as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registersPeter Maydell
Add implementations of the AMAIR0 and AMAIR1 LPAE Auxiliary Memory Attribute Indirection Registers. These are implementation defined and we choose to implement them as RAZ/WI, matching the Cortex-A7 and Cortex-A15. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Extend feature flags to 64 bitsPeter Maydell
Extend feature flags to 64 bits, as we've just run out of space in the 32 bit integer we were using for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Implement privileged-execute-never (PXN)Peter Maydell
Implement the privileged-execute-never (PXN) translation table bit. It is implementation-defined whether this is implemented, so we give it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an LPAE feature flag and the implication logic, as a placeholder for actually implementing LPAE at a later date. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bitsPeter Maydell
Make target_phys_addr_t 64 bits for ARM targets, and set TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM boards where physical addresses really are 32 bits (except perhaps a slight performance hit on 32 bit hosts for system emulation) but allows us to implement the Large Physical Address Extensions for Cortex-A15, which mean 40 bit physical addresses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bitsPeter Maydell
Add a missing cast to avoid gcc complaining about format string errors when printing an expression based on a target_phys_addr_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Chubb <peter.chubb@nicta.com.au>
2012-07-12target-arm: Fix TCG temp handling in 64 bit cp writesPeter Maydell
Fix errors in the TCG temp handling in the 64 bit coprocessor write path: we were reusing a 32 bit temp after it had been freed by store_reg(), and failing to free a 64 bit temp. This bug has no visible effect at this point because there aren't any non-NOP 64 bit registers yet; it needs to be fixed as a prerequisite for the 64 bit registers in LPAE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Fix some copy-and-paste errors in cp register namesPeter Maydell
Fix a couple of cases where cp register names were copy-and-pasted. These are harmless since we don't use the name for anything (except debugging convenience) but could be confusing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-07-12target-arm: Fix typo that meant TTBR1 accesses went to TTBR0Peter Maydell
Fix a copy-and-paste error in the register description for TTBR1 that meant it was a duplicate of TTBR0 rather than affecting the correct bit of CPU state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Fix CP15 based WFIPaul Brook
The coprocessor register rework broke cp15 based WFI instructions. We incorrectly fall through the normal register write case, which incorrectly adds a forced block termination. We've already done a special version of this (DISAS_WFI), so return immediately. Signed-off-by: Paul Brook <paul@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-11iov: Fix do_send_recv() for MinGW (also fixes a build breakage)Stefan Weil
Commit 25e5e4c7 broke compilation for non POSIX hosts (e.g. MinGW) because it partially replaced "ret" by "count". It also changed the handling of EINTR in a wrong way. The patch restores the old code for these two changes. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-07-11qemu_find_file: check name as a straight path even if it has no '/'Peter Maydell
Make qemu_find_file() check for the passed in name as a straight pathname even if it doesn't have any path separator character in it. This means that "-bios foo", "-dtb foo" etc will find a file 'foo' in the current directory. This removes an inconsistency with -kernel and -initrd, which both accept plain filenames as meaning files in the current directory. It's also less confusing for the user than an undocumented restriction that "this option accepts a filename, except for the special case where the filename you pass happens not to have a '/' in it, in which case we'll ignore it." Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>