aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2013-12-06target-arm: A64: add support for logical (immediate) insnsa64-second-setAlexander Graf
This patch adds support for C3.4.4 Logical (immediate), which include AND, ANDS, ORR, EOR. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, function renaming, removed a TCG temp variable] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: cleaned up some unnecessary code in logic_imm_decode_wmask and added clarifying commentary on what it's actually doing. Dropped an ext32u that's not needed if we've just done an AND.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for 1-src CLS insnClaudio Fontana
this patch adds support for the CLS instruction. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06host-utils: add clrsb32/64 - count leading redundant sign bitsClaudio Fontana
this patch introduces wrappers for the clrsb builtins, which count the leading redundant sign bits. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for bitfield insnsClaudio Fontana
This patch implements the C3.4.2 Bitfield instructions: SBFM, BFM, UBFM. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for 1-src REV insnsClaudio Fontana
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for 1-src RBIT insnAlexander Graf
This adds support for the C5.6.147 RBIT instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch, splitting REV into a separate patch] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana
This patch adds support for decoding 1-src data processing insns, and the first user, C5.6.40 CLZ (count leading zeroes). Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for 2-src shift reg insnsAlexander Graf
This adds 2-src variable shift register instructions: C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use enums for shift types] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for 2-src data processing and DIVAlexander Graf
This patch adds support for decoding 2-src data processing insns, and the first users, UDIV and SDIV. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder adding the 2-src decoding level, always zero-extend result in 32bit mode] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for EXTRAlexander Graf
This patch adds emulation support for the EXTR instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more unallocated cases] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for ADR and ADRPAlexander Graf
Add support for the instructions described in "C3.4.6 PC-rel. addressing" (ADR and ADRP). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-06target-arm: A64: add support for logical (shifted register)Alexander Graf
Add support for the instructions described in "C3.5.10 Logical (shifted register)". We store the flags in the same locations as the 32 bit decoder. This is slightly awkward when calculating 64 bit results, but seems a better tradeoff than having to rework the whole 32 bit decoder and also make 32 bit result calculation in A64 awkward. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: some refactoring to avoid hidden allocation of temps, rework flags, use enums for shift types, renaming of functions] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-05target-arm: A64: add support for conditional selectClaudio Fontana
This patch adds support for the instruction group "C3.5.6 Conditional select": CSEL, CSINC, CSINV, CSNEG. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: Improved code generated in the nomatch case as per RTH suggestions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-05target-arm: A64: add support for compare and branch immAlexander Graf
This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-05target-arm: A64: add support for 'test and branch' immAlexander Graf
This patch adds emulation for the test and branch insns, TBZ and TBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder always compare with 0 remove a TCG temporary ] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-05target-arm: A64: add support for conditional branchesAlexander Graf
This patch adds emulation for the conditional branch (b.cond) instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-05target-arm: A64: add support for BR, BLR and RET insnsAlexander Graf
Implement BR, BLR and RET. This is all of the 'unconditional branch (register)' instruction category except for ERET and DPRS (which are system mode only). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: reimplemented on top of new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-04target-arm: A64: add support for B and BL insnsAlexander Graf
Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the end of decode of the instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: renamed functions, adapted to new decoder layout] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-04target-arm: A64: expand decoding skeleton for system instructionsClaudio Fontana
Decode the various kinds of system instructions: hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL sync instructions, which include CLREX, DSB, DMB, ISB msr_i, which move immediate to processor state field sys, which include all SYS and SYSL instructions msr, which move from a gp register to a system register mrs, which move from a system register to a gp register Provide implementations where they are trivial nops. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-04target-arm: A64: provide skeleton for a64 insn decodingClaudio Fontana
Provide a skeleton for a64 instruction decoding in translate-a64.c, by dividing instructions into the classes defined by the ARM Architecture Reference Manual(DDI0487A_a) section C3. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-04target-arm: A64: add stubs for a64 specific helpersAlexander Graf
We will need helpers that only make sense with AArch64. Add helper-a64.{c,h} files as stubs that we can fill with these helpers in the following patches. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-04target-arm: Support fp registers in gdb stubPeter Maydell
Register the aarch64-fpu XML and implement the necessary read/write handlers so we can support reading and writing of FP registers in the gdb stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-04target-arm: A64: provide functions for accessing FPCR and FPSRPeter Maydell
The information which AArch32 holds in the FPSCR is split for AArch64 into two logically distinct registers, FPSR and FPCR. Since they are carefully arranged to use non-overlapping bits, we leave the underlying state in the same place, and provide accessor functions which just update the appropriate bits via vfp_get_fpscr() and vfp_set_fpscr(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-04target-arm: A64: add set_pc cpu methodAlexander Graf
When executing translation blocks we need to be able to recover our program counter. Add a method to set it for AArch64 CPUs. This covers user-mode, but for system mode emulation we will need to check if the CPU is in an AArch32 execution state. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-03target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell
The A32/T32 gen_intermediate_code_internal() is complicated because it has to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing None of these apply to A64, so putting the "this is A64 so call the A64 decoder" check in the middle of the A32/T32 loop is confusing and means the A64 decoder's handling of things like conditional jump and singlestepping has to take account of the conditional-execution jumps the main loop might emit. Refactor the code to give A64 its own gen_intermediate_code_internal function instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-11-27default-configs: Add config for aarch64-softmmumach-virt-64Peter Maydell
Add a config for aarch64-softmmu; this enables building of this target. The resulting executable doesn't know about any 64 bit CPUs, but all the 32 bit CPUs and board models work. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27hw/arm/boot: Add boot support for AArch64 processorMian M. Hamayun
This commit adds support for booting a single AArch64 CPU by setting appropriate registers. The bootloader includes placehoders for Board-ID that are used to implement uniform indexing across different bootloaders. Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> [PMM: * updated to use ARMInsnFixup style bootloader fragments * dropped virt.c additions * use runtime checks for "is this an AArch64 core" rather than ifdefs * drop some unnecessary setting of registers in reset hook ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27hw/arm/boot: Allow easier swapping in of different loader codePeter Maydell
For AArch64 we will obviously require a different set of primary and secondary boot loader code fragments. However currently we hardcode the offsets into the loader code where we must write the entrypoint and other data into arm_load_kernel(). This makes it hard to substitute a different loader fragment, so switch to a more flexible scheme where instead of a raw array of instructions we use an array of (instruction, fixup-type) pairs that indicate which words need special action or data written into them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27configure: Enable KVM for aarch64 host/target combinationPeter Maydell
Enable KVM if the host and target CPU are both aarch64. Note that host aarch64 + target arm is not valid for KVM acceleration: the 64 bit kernel does not support the ioctl interface for 32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created using the 64 bit ioctl interface; when QEMU supports this it will be on the arch64-softmmu target with a -cpu parameter for a 32 bit CPU, which is still an aarch64/aarch64 combination as far as configure is concerned. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27target-arm: Add minimal KVM AArch64 supportMian M. Hamayun
Add the bare minimum set of functions needed for control of an AArch64 KVM vcpu: * CPU initialization * minimal get/put register functions which only handle the basic state of the CPU Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> [PMM: significantly overhauled; most notably: * code lives in kvm64.c rather than using #ifdefs * support '-cpu host' rather than implicitly using whatever the host's CPU is regardless of what the user requests * fix bug attempting to get/set nonexistent X[31] * fix bug writing 64 bit kernel pstate into uint32_t env field ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-26target-arm: Clean up handling of AArch64 PSTATEPeter Maydell
The env->pstate field is a little odd since it doesn't strictly speaking represent an architectural register. However it's convenient for QEMU to use it to hold the various PSTATE architectural bits in the same format the architecture specifies for SPSR registers (since this is the same format the kernel uses for signal handlers and the KVM register). Add some structure to how we deal with it: * document what env->pstate is * add some #defines for various bits in it * add helpers for reading/writing it taking account of caching of NZCV, and use them where appropriate * reset it on startup Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22target-arm/kvm: Split 32 bit only code into its own filePeter Maydell
Split ARM KVM support code which is 32 bit specific out into its own file, which we only compile on 32 bit hosts. This will give us a place to add the 64 bit support code without adding lots of ifdefs to kvm.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22hw/arm/virt: Support -cpu hostmach-virtPeter Maydell
Support -cpu host in virt machine (treating it like an A15, ie with a GIC v2 and the A15's private peripherals.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22target-arm: Provide '-cpu host' when running KVMPeter Maydell
Implement '-cpu host' for ARM when we're using KVM, broadly in line with other KVM-supporting architectures. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22target-arm: Don't hardcode KVM target CPU to be A15Peter Maydell
Instead of assuming that a KVM target CPU must always be a Cortex-A15 and hardcoding this in kvm_arch_init_vcpu(), store the KVM_ARM_TARGET_* value in the ARMCPU class, and use that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22linux-headers: Update from mainlinePeter Maydell
Update Linux KVM headers from mainline commit 5d6e63323fe779. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22hw/arm: Add 'virt' platformPeter Maydell
Add 'virt' platform support corresponding to arch/arm/mach-virt in the Linux kernel tree. This has no platform-specific code but can use any device whose kernel driver is is able to work purely from a device tree node. We use this to instantiate a minimal set of devices: a GIC and some virtio-mmio transports. Signed-off-by: John Rigby <john.rigby@linaro.org> [PMM: Significantly overhauled: * renamed user-facing machine to just "virt" * removed the A9 support (it can't work since the A9 has no generic timers) * added virtio-mmio transports instead of random set of 'soc' devices (though we retain a pl011 UART) * instead of updating io_base as we step through adding devices, define a memory map with an array (similar to vexpress) * similarly, define irqmap with an array * folded in some minor fixes from John's aarch64-support patch * rather than explicitly doing endian-swapping on FDT cells, use fdt APIs that let us just pass in host-endian values and let the fdt layer take care of the swapping * miscellaneous minor code cleanups and style fixes ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22target-arm: Allow secondary KVM CPUs to be booted via PSCIPeter Maydell
New ARM boards are generally expected to boot their secondary CPUs via the PSCI interface, rather than ad-hoc "loop around in holding pen code" as hw/arm/boot.c implements. In particular this is necessary for mach-virt kernels. For KVM we achieve this by creating the VCPUs with a feature flag marking them as starting in PSCI powered-down state; the guest kernel will then make a PSCI call (implemented in the host kernel) to start the secondaries at an address of its choosing once it has got the primary CPU up. Implement this setting of the feature flag, controlled by a qdev property for ARMCPU, which board code can set if it is a PSCI system. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22target-arm: Add ARMCPU field for Linux device-tree 'compatible' stringPeter Maydell
Linux requires device tree CPU nodes to include a 'compatible' string describing the CPU. Add a field in the ARMCPU struct for this so that boards which construct a device tree can insert the correct CPU nodes. Note that there is currently no officially specified 'compatible' string for the TI925T, Cortex-M3 or SA1110 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22target-arm: Provide PSCI constants to generic QEMU codePeter Maydell
Provide versions of the KVM PSCI constants to non-KVM code; this will allow us to avoid an ifdef in boards which set up a PSCI node in the device tree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22hw/arm/boot: Allow boards to provide an fdt blobJohn Rigby
If no fdt is provided on command line and the new field get_dtb in struct arm_boot_info is set then call it to get a device tree blob. Signed-off-by: John Rigby <john.rigby@linaro.org> [PMM: minor tweaks and cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-22device_tree.c: Terminate the empty reservemap in create_device_tree()Peter Maydell
Device trees created with create_device_tree() may not have any entries in their reservemap, because the FDT API requires that the reservemap is completed before any FDT nodes are added, and create_device_tree() itself creates a node. However we were not calling fdt_finish_reservemap(), which meant that there was no terminator in the reservemap list and whatever happened to be at the start of the FDT data section would end up being interpreted as reservemap entries. Avoid this by calling fdt_finish_reservemap() to add the terminator. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alexander Graf <agraf@suse.de>
2013-11-22target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVMPeter Maydell
There are a number of places where it would be convenient for ARM code to have working definitions of KVM constants even in code which is compiled with CONFIG_KVM not set. In this situation we can't simply include the kernel KVM headers (which might conflict with host header definitions or not even compile on the compiler we're using) so we have to redefine equivalent constants. Provide a mechanism for doing this and checking that the values match, and use it for the constants we're currently exposing via an ad-hoc mechanism. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-21Update version for 1.7.0-rc1 releaseAnthony Liguori
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21vfio-pci: Fix multifunction=onAlex Williamson
When an assigned device is initialized it copies the device config space into the emulated config space. Unfortunately multifunction is setup prior to the device initfn and gets clobbered. We need to restore it just like pci-assign does. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Bandan Das <bsd@redhat.com> Message-id: 20131112185059.7262.33780.stgit@bling.home Cc: qemu-stable@nongnu.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21target-i386: Fix addr32 prefix in gen_lea_modrmRichard Henderson
Fix the following run-test-x86_64 testsuite failures: -lea (%%eax) = 0000000000000001 -lea (%%ebx) = 0000000000000002 -lea (%%ecx) = 0000000000000004 -lea (%%edx) = 0000000000000008 -lea (%%esi) = 0000000000000010 -lea (%%edi) = 0000000000000020 +lea (%%eax) = 0000abcc00000001 +lea (%%ebx) = 0000abcf00000002 +lea (%%ecx) = 0000abc900000004 +lea (%%edx) = 0000abc500000008 +lea (%%esi) = 0000abdd00000010 +lea (%%edi) = 0000abed00000020 In addition, reduce ifdeffery and minimize the number of TCG ops produced during address computation. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1384219016-5170-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21atomic.h: Fix build with clangPeter Maydell
clang defines __ATOMIC_SEQ_CST but its implementation of the __atomic_exchange() builtin differs from that of gcc. Move the __clang__ branch of the ifdef ladder to the top and fix its implementation (there is no such builtin as __sync_exchange), so we can compile with clang again. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1382435921-18438-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21target-i386: do not override nr_cores for -cpu hostPaolo Bonzini
Commit 787aaf5 (target-i386: forward CPUID cache leaves when -cpu host is used, 2013-09-02) brings bits 31..26 of CPUID leaf 04h out of sync with the APIC IDs that QEMU reserves for each package. This number must come from "-smp" options rather than from the host CPUID. It also turns out that this unsyncing makes Windows Server 2012R2 fail to boot. Tested-by: Peter Lieven <pl@kamp.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Benoit Canet <benoit@irqsave.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 1384879786-6721-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21mips jazz: do not raise data bus exception when accessing invalid addressesHervé Poussineau
MIPS Jazz chipset doesn't seem to raise data bus exceptions on invalid accesses. However, there is no easy way to prevent them. Creating a big memory region for the whole address space doesn't prevent memory core to directly call unassigned_mem_read/write which in turn call cpu->do_unassigned_access, which (for MIPS CPU) raise an data bus exception. This fixes a MIPS Jazz regression introduced in c658b94f6e8c206c59d02aa6fbac285b86b53d2c. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-id: 1383603977-7003-1-git-send-email-hpoussin@reactos.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21target-i386: yield to another VCPU on PAUSEPaolo Bonzini
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown. The problem shows up as soon as FreeBSD turns out its periodic (~1 ms) tick, but the timers are only the trigger for a pre-existing problem. Before the offending patch, setting a timer did a timer_settime system call. After, setting the timer exits the event loop (which uses poll) and reenters it with a new deadline. This does not cause any slowdown; the difference is between one system call (timer_settime and a signal delivery (SIGALRM) before the patch, and two system calls afterwards (write to a pipe or eventfd + calling poll again when re-entering the event loop). Unfortunately, the exit/enter causes the main loop to grab the iothread lock, which in turns kicks the VCPU thread out of execution. This causes TCG to execute the next VCPU in its round-robin scheduling of VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause" instruction in its idle loop which only burns cycles without any progress. As soon as the timer tick expires, the first VCPU runs the interrupt handler but very soon it sets it again---and QEMU then goes back doing nothing in the second VCPU. The fix is to make the pause instruction do "cpu_loop_exit". Cc: Richard Henderson <rth@twiddle.net> Reported-by: Luigi Rizzo <rizzo@iet.unipi.it> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>