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2013-12-03add ldp/stp vector formsa64-first-set-test-contextPeter Maydell
ldp/stp decode wasn't checking the vector bit, so we wrote the int regs by mistake for LDP d8,d9,[sp,#96] Add support. Note to Alex: we really should fold the load and store support together better, most of the decode is the same at the bottom level. Possibly factoring out the 'if vector do_fp_st else do_gpr_st' logic as the suse patches do would also be a good plan. I've left some XXX notes about updating comments in this one. Oh yes, we should check the semantics for what happens if the second load of the pair faults -- currently we update the first register, but I have a feeling maybe we should not.
2013-12-03target-arm: A64: Floating point <-> integer convPeter Maydell
This is kinda from suse patch 52 but I ended up rewriting it pretty thoroughly and with a view to comments made on the mailing list w.r.t the silliness of double stores to the fpu reg memory). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Inspired-by: Alexander Graf <agraf@suse.de> aarch64 series 52/60
2013-12-03target-arm: A64: TODO Data processing (3 source)Peter Maydell
Add support for various 3 source data processing instructions. From Alexander Graf <agraf@suse.de> aarch64 series 49/60 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> --- TODO fix up attributions, commit message v3 -> v4 (pmm): - ported to into new decoder - cleaned up to match current fn name conventions
2013-12-03target-arm: A64: XXX support for ldaxr and relatedPeter Maydell
XXX: not up-streamable as is I've fixed up the decoding but this is a no-op version of exclusives so is definitely not upstreamable. Needs rewrite. From Alexander Graf <agraf@suse.de> aarch64 series 12/60
2013-12-03target-arm: aarch64: add support for svc instructionAlex Bennée
This patch adds emulation for the syscall (svc) instruction. Signed-off-by: Alexander Graf <agraf@suse.de> --- v2 -> v3: - use extract32/sextract32 instead of get_bits and get_sbits v3 -> v4 (ajb): - ported to new decode skeleton v4 -> v5 (ajb): - fixed stupid decode error v5 -> v6 (ajb): - fix svc from peters tree.
2013-12-03target-arm: aarch64: add support for ldp (load pair)Alex Bennée
This uses the existing GPR load routines to do the actual load. This was split out from the more substantial ldarx implementation. from Alexander Graf <agraf@suse.de> aarch64 series 12/60 --- v3 -> v4 (pmm): - Fix offset calculation in ldp
2013-12-03target-arm: A64: add support for ld/st with indexAlex Bennée
This adds support for the pre/post-index ld/st forms with immediate offsets as well as the un-scaled immediate form. This was split out of the original patch due to re-factoring changes. from Alexander Graf <agraf@suse.de> aarch64 series 41/60 --- v3 -> v4 (ajb) - fix ld/st reg indexed_imm to correctly extend and shift v4 -> v5 (ajb): - fix silly bug with extracting register v5 -> v6 (pmm): - move is_vector test into handler. v6 -> v7 (pmm): - add un-scaled imm9 version NOTES: I suspect we're going to want to fold the 'load/store unprivileged' insns into the same imm9 decode, so I have left the door open for that. However since we shouldn't see those for userspace code we can ignore it for the moment. -- PMM
2013-12-03target-arm: A64: add support for ld/st with reg offsetAlex Bennée
This adds support for the load/store forms using a register offset. This was split out from the original patch due to re-factoring changes. from Alexander Graf <agraf@suse.de> aarch64 series 41/60 --- v3 -> v4 (ajb): fixed reg extension v4 -> v5 (pmm): moved is_vector test into handle func fix invalid asset on opt==6 v5 -> v6 (ajb): fix temp lead in handle_ldst_reg_roffset
2013-12-03target-arm: aarch64: add support for ld litAlex Bennée
Adds support for Load Register (literal). from Alexander Graf <agraf@suse.de> aarch64 series 40/60
2013-12-03target-arm: A64: add support for ld/st unsigned immAlex Bennée
This adds support for the basic forms of ld/st with an unsigned immediate offset. This was split from the original patch from Alexander due to re-factoring due to the changes in the decoder. This includes the helper function: * do_gpr_ld * do_fp_st * do_fp_ld from Alexander Graf <agraf@suse.de> aarch64 series 41/60 --- v3 -> v4 (pmm): - hoisted is_vector test into function v4 -> v5 (pmm): - added support for ld/st of FP regs - fixed some tcg temp leaks
2013-12-03target-arm: aarch64: add support for moviAlex Bennée
This patch adds emulation for the movi instruction. This includes the various movn, movz and movk forms. Signed-off-by: Alexander Graf <agraf@suse.de> --- v2 -> v3: - use extract32/sextract32 instead of get_bits and get_sbits - open code get_reg() v3 -> v4 (ajb): - applied RH's constant folding comment - move cpu_reg allocation to top
2013-12-03target-arm: A64: add support for stp (store pair)Alex Bennée
This patch support basic GPR based store-pair instructions and includes the generic do_gpr_st() function for store routines. This include a helper function: * do_gpr_st() from Alexander Graf <agraf@suse.de> aarch64 series 11/60 --- v2 -> v3: - use extract32/sextract32 instead of get_bits and get_sbits - drop get_reg() - open code get_reg() v3 -> v4 - split from bigger patch (non vector) - better naming?
2013-12-03target-arm: A64: add support for add and addiAlex Bennée
This patch combines two of the original series for generic add implementation support. It includes some additional helper functions that will be useful elsewhere: * ext_and_shift_reg for register extension (with opt shift) * read_cpu_reg_sp (sp version of read_cpu_reg) * gen_set_ZN/ZN64 for setting Z and N flags * gen_add/sub_CC for generic arithmetic with flag setting from Alexander Graf <agraf@suse.de> aarch64 series 15/60 (- extended) from Alexander Graf <agraf@suse.de> aarch64 series 27/60 from Alexander Graf <agraf@suse.de> aarch64 series 60/60 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- v2 -> v3: - use extract32/sextract32 instead of get_bits and get_sbits - open code get_reg() v3 -> v4 (ajb): - removed the flag handling helpers, stubbed out TCG equivalent - streamlined the generation to avoid duplication v4 -> v5 (ajb): - used Claudio's common add_with_carry for flag ops - common as much as possible between addi/add - removed extraneous diagrams - documented the add (extended register) stub v5 -> v6 (ajb): - drop add_with_carry for now v6 -> v7 (ajb): - fixed dodgy tcg generation. v7 -> v8 (ajb): - fixed merge conflicts with cpu_reg_sp() - used Claudio's generic flag helpers - add ext_and_shift_reg helper for extension - rename disas->handle for actual implementations - include add_sub_extended_reg v8 -> v9 (ajb): - actually use extended register for offset v9 -> v10 (ajb): - add CC support to add_sub_reg v10 -> v11 (pmm): - split arith_CC into gen_add/sub_cc functions - rewrite with newer version of flag code v11 -> v12 (ajb): - move to using the new read_cpu_reg helper. Conflicts: target-arm/translate-a64.c Conflicts: target-arm/translate-a64.c
2013-12-03translate-a64.c: add a debug helper trace macroAlex Bennée
This just makes it easier to drop TRACE_DECODE statements all over the place instead of fprintfs.
2013-12-03linux-user/signal.c: dump pc when abortingAlex Bennée
It doesn't hurt and it certainly helps when bringing up new instructions when it breaks.
2013-12-03.travis.yml: add aarch64-linux-user targetAlex Bennée
2013-12-03default-configs: Add config for aarch64-linux-userPeter Maydell
Add a config for aarch64-linux-user, thereby enabling it as a valid target. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-03target-arm: A64: MRS/MSR for FPCR accessClaudio Fontana
Add FPCR to the set of registers handled by MRS/MSR; implemented via calls to helper functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
2013-12-03target-arm: A64: add preliminary support for MSR/MRSClaudio Fontana
this is very very limited: we only support setting and getting NZCV (C4.3.10), getting CTR_EL0 (D8.2.21) with a hardcoded value, getting DCZID_EL0 (D8.2.23) with a hardcoded value, getting and setting TPIDR_EL0 (D8.2.87). Eventually this could be rewritten on top of arm_cp_regs API with some refactoring necessary (main issue: ARM_CP_64BIT) Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure, put common code between MSR/MRS in a separate function, add NZCV, add support for writing to TPIDR_EL0, fixed high bit of CTR_EL0] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> from Alexander Graf <agraf@suse.de> aarch64 series 35/60, 36/60
2013-12-03target-arm: A64: add support for logical (immediate) insnsClaudio Fontana
this patch adds support for C3.4.4 Logical (immediate), which include AND, ANDS, ORR, EOR. It also includes a way to access the registers when register 31 means SP. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, minor function renaming, removed a TCG temp variable] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 29/60
2013-12-03target-arm: A64: add support for 1-src CLS insnClaudio Fontana
this patch adds support for the CLS instruction. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From the SUSE patches
2013-12-03host-utils: add clrsb32/64 - count leading redundant sign bitsClaudio Fontana
this patch introduces wrappers for the clrsb builtins, which count the leading redundant sign bits. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
2013-12-03target-arm: A64: add support for bitfield insnsClaudio Fontana
this patch supports C3.4.2 Bitfield instructions SBFM, BFM, UBFM. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 31/60
2013-12-03target-arm: A64: add support for 1-src REV insnsClaudio Fontana
this adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 46/60
2013-12-03target-arm: A64: add support for 1-src RBIT insnClaudio Fontana
this adds support for the C5.6.147 RBIT instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch, will handle REV in a separate patch] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 46/60
2013-12-03target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana
this patch adds support for decoding 1-src data processing insns, and the first user, C5.6.40 CLZ(count leading zeroes). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, simpler path for 64bit form, reuse 32bit helper for 32bit form] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 47/60
2013-12-03target-arm: A64: add support for 2-src shift reg insnsClaudio Fontana
this adds 2-src variable shift register instructions C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 45/60
2013-12-03target-arm: A64: add support for 2-src data processing and DIVClaudio Fontana
this patch adds support for decoding 2-src data processing insns, and the first users, UDIV and SDIV. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder adding the 2-src decoding level, always zero-extend result in 32bit mode] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
2013-12-03target-arm: A64: add support for EXTRClaudio Fontana
This patch adds emulation support for the EXTR instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more unallocated cases] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 30/60
2013-12-03target-arm: A64: add support for ADR and ADRPClaudio Fontana
this adds support for the instructions described in: C3.4.6 PC-rel. addressing (ADR and ADRP). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> from Alexander Graf <agraf@suse.de> aarch64 series 26/60
2013-12-03target-arm: A64: add support for logical (shifted register)Claudio Fontana
this adds support for the instructions described in: C3.5.10 Logical (shifted register) Support includes a reworking of flags, and a way to read the registers in copy mode that also zero extends on 32bit access. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> from Alexander Graf <agraf@suse.de> aarch64 series 14/60
2013-12-03target-arm: A64: add support for conditional selectClaudio Fontana
This patch adds support for "C3.5.6 Conditional select", which means CSEL, CSINC, CSINV, CSNEG. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> From Alexander Graf <agraf@suse.de> aarch64 series 43/60
2013-12-03target-arm: A64: add support for compare and branch immAlexander Graf
This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: add support for 'test and branch' immAlexander Graf
This patch adds emulation for the test and branch insns, TBZ and TBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder always compare with 0 remove a TCG temporary ] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: add support for conditional branchesAlexander Graf
This patch adds emulation for the conditional branch (b.cond) instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: add support for BR, BLR and RET insnsAlexander Graf
Implement BR, BLR and RET. This is all of the 'unconditional branch (register)' instruction category except for ERET and DPRS (which are system mode only). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: reimplemented on top of new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: add support for B and BL insnsAlexander Graf
Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the end of decode of the instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: renamed functions, adapted to new decoder layout] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: expand decoding skeleton for system instructionsClaudio Fontana
Decode the various kinds of system instructions: hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL sync instructions, which include CLREX, DSB, DMB, ISB msr_i, which move immediate to processor state field sys, which include all SYS and SYSL instructions msr, which move from a gp register to a system register mrs, which move from a system register to a gp register Provide implementations where they are trivial nops. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: provide skeleton for a64 insn decodingClaudio Fontana
Provide a skeleton for a64 instruction decoding in translate-a64.c, by dividing instructions into the classes defined by the ARM Architecture Reference Manual(DDI0487A_a) section C3. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: add stubs for a64 specific helpersAlexander Graf
We will need helpers that only make sense with AArch64. Add helper-a64.{c,h} files as stubs that we can fill with these helpers in the following patches. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: Support fp registers in gdb stubPeter Maydell
Register the aarch64-fpu XML and implement the necessary read/write handlers so we can support reading and writing of FP registers in the gdb stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: provide functions for accessing FPCR and FPSRPeter Maydell
The information which AArch32 holds in the FPSCR is split for AArch64 into two logically distinct registers, FPSR and FPCR. Since they are carefully arranged to use non-overlapping bits, we leave the underlying state in the same place, and provide accessor functions which just update the appropriate bits via vfp_get_fpscr() and vfp_set_fpscr(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: A64: add set_pc cpu methodAlexander Graf
When executing translation blocks we need to be able to recover our program counter. Add a method to set it for AArch64 CPUs. This covers user-mode, but for system mode emulation we will need to check if the CPU is in an AArch32 execution state. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-03target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell
The A32/T32 gen_intermediate_code_internal() is complicated because it has to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing None of these apply to A64, so putting the "this is A64 so call the A64 decoder" check in the middle of the A32/T32 loop is confusing and means the A64 decoder's handling of things like conditional jump and singlestepping has to take account of the conditional-execution jumps the main loop might emit. Refactor the code to give A64 its own gen_intermediate_code_internal function instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27default-configs: Add config for aarch64-softmmumach-virt-64Peter Maydell
Add a config for aarch64-softmmu; this enables building of this target. The resulting executable doesn't know about any 64 bit CPUs, but all the 32 bit CPUs and board models work. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27hw/arm/boot: Add boot support for AArch64 processorMian M. Hamayun
This commit adds support for booting a single AArch64 CPU by setting appropriate registers. The bootloader includes placehoders for Board-ID that are used to implement uniform indexing across different bootloaders. Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> [PMM: * updated to use ARMInsnFixup style bootloader fragments * dropped virt.c additions * use runtime checks for "is this an AArch64 core" rather than ifdefs * drop some unnecessary setting of registers in reset hook ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27hw/arm/boot: Allow easier swapping in of different loader codePeter Maydell
For AArch64 we will obviously require a different set of primary and secondary boot loader code fragments. However currently we hardcode the offsets into the loader code where we must write the entrypoint and other data into arm_load_kernel(). This makes it hard to substitute a different loader fragment, so switch to a more flexible scheme where instead of a raw array of instructions we use an array of (instruction, fixup-type) pairs that indicate which words need special action or data written into them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27configure: Enable KVM for aarch64 host/target combinationPeter Maydell
Enable KVM if the host and target CPU are both aarch64. Note that host aarch64 + target arm is not valid for KVM acceleration: the 64 bit kernel does not support the ioctl interface for 32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created using the 64 bit ioctl interface; when QEMU supports this it will be on the arch64-softmmu target with a -cpu parameter for a 32 bit CPU, which is still an aarch64/aarch64 combination as far as configure is concerned. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-27target-arm: Add minimal KVM AArch64 supportMian M. Hamayun
Add the bare minimum set of functions needed for control of an AArch64 KVM vcpu: * CPU initialization * minimal get/put register functions which only handle the basic state of the CPU Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> [PMM: significantly overhauled; most notably: * code lives in kvm64.c rather than using #ifdefs * support '-cpu host' rather than implicitly using whatever the host's CPU is regardless of what the user requests * fix bug attempting to get/set nonexistent X[31] * fix bug writing 64 bit kernel pstate into uint32_t env field ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-26target-arm: Clean up handling of AArch64 PSTATEPeter Maydell
The env->pstate field is a little odd since it doesn't strictly speaking represent an architectural register. However it's convenient for QEMU to use it to hold the various PSTATE architectural bits in the same format the architecture specifies for SPSR registers (since this is the same format the kernel uses for signal handlers and the KVM register). Add some structure to how we deal with it: * document what env->pstate is * add some #defines for various bits in it * add helpers for reading/writing it taking account of caching of NZCV, and use them where appropriate * reset it on startup Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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