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-rw-r--r--target/riscv/meson.build34
1 files changed, 34 insertions, 0 deletions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
new file mode 100644
index 0000000000..abd647fea1
--- /dev/null
+++ b/target/riscv/meson.build
@@ -0,0 +1,34 @@
+# FIXME extra_args should accept files()
+dir = meson.current_source_dir()
+gen32 = [
+ decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+ decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+]
+
+gen64 = [
+ decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+ decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
+]
+
+riscv_ss = ss.source_set()
+riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
+riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
+riscv_ss.add(files(
+ 'cpu.c',
+ 'cpu_helper.c',
+ 'csr.c',
+ 'fpu_helper.c',
+ 'gdbstub.c',
+ 'op_helper.c',
+ 'vector_helper.c',
+ 'translate.c',
+))
+
+riscv_softmmu_ss = ss.source_set()
+riscv_softmmu_ss.add(files(
+ 'pmp.c',
+ 'monitor.c'
+))
+
+target_arch += {'riscv': riscv_ss}
+target_softmmu_arch += {'riscv': riscv_softmmu_ss}