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Diffstat (limited to 'target/microblaze/translate.c')
-rw-r--r--target/microblaze/translate.c211
1 files changed, 74 insertions, 137 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a14ffed784..fc451befae 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -24,13 +24,16 @@
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
#include "exec/helper-gen.h"
#include "exec/translator.h"
#include "qemu/qemu-print.h"
#include "exec/log.h"
+#define HELPER_H "helper.h"
+#include "exec/helper-info.c.inc"
+#undef HELPER_H
+
#define EXTRACT_FIELD(src, start, end) \
(((src) >> start) & ((1 << (end - start + 1)) - 1))
@@ -54,16 +57,11 @@ static TCGv_i32 cpu_iflags;
static TCGv cpu_res_addr;
static TCGv_i32 cpu_res_val;
-#include "exec/gen-icount.h"
-
/* This is the state at translation time. */
typedef struct DisasContext {
DisasContextBase base;
const MicroBlazeCPUConfig *cfg;
- /* TCG op of the current insn_start. */
- TCGOp *insn_start;
-
TCGv_i32 r0;
bool r0_set;
@@ -101,10 +99,7 @@ static void t_sync_flags(DisasContext *dc)
static void gen_raise_exception(DisasContext *dc, uint32_t index)
{
- TCGv_i32 tmp = tcg_const_i32(index);
-
- gen_helper_raise_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}
@@ -117,21 +112,15 @@ static void gen_raise_exception_sync(DisasContext *dc, uint32_t index)
static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
{
- TCGv_i32 tmp = tcg_const_i32(esr_ec);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr));
- tcg_temp_free_i32(tmp);
+ TCGv_i32 tmp = tcg_constant_i32(esr_ec);
+ tcg_gen_st_i32(tmp, tcg_env, offsetof(CPUMBState, esr));
gen_raise_exception_sync(dc, EXCP_HW_EXCP);
}
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
{
- if (dc->base.singlestep_enabled) {
- TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
- tcg_gen_movi_i32(cpu_pc, dest);
- gen_helper_raise_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
- } else if (translator_use_goto_tb(&dc->base, dest)) {
+ if (translator_use_goto_tb(&dc->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_exit_tb(dc->base.tb, n);
@@ -267,11 +256,9 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,
rd = reg_for_write(dc, arg->rd);
ra = reg_for_read(dc, arg->ra);
- imm = tcg_const_i32(arg->imm);
+ imm = tcg_constant_i32(arg->imm);
fn(rd, ra, imm);
-
- tcg_temp_free_i32(imm);
return true;
}
@@ -305,33 +292,28 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,
#define ENV_WRAPPER2(NAME, HELPER) \
static void NAME(TCGv_i32 out, TCGv_i32 ina) \
- { HELPER(out, cpu_env, ina); }
+ { HELPER(out, tcg_env, ina); }
#define ENV_WRAPPER3(NAME, HELPER) \
static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \
- { HELPER(out, cpu_env, ina, inb); }
+ { HELPER(out, tcg_env, ina, inb); }
/* No input carry, but output carry. */
static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero);
-
- tcg_temp_free_i32(zero);
}
/* Input and output carry. */
static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero);
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
-
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(zero);
}
/* Input carry, but no output carry. */
@@ -366,7 +348,6 @@ static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_sar_i32(out, ina, tmp);
- tcg_temp_free_i32(tmp);
}
static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
@@ -374,7 +355,6 @@ static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_shr_i32(out, ina, tmp);
- tcg_temp_free_i32(tmp);
}
static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
@@ -382,7 +362,6 @@ static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_shl_i32(out, ina, tmp);
- tcg_temp_free_i32(tmp);
}
static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm)
@@ -441,7 +420,6 @@ static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina);
tcg_gen_sub_i32(out, inb, ina);
tcg_gen_deposit_i32(out, out, lt, 31, 1);
- tcg_temp_free_i32(lt);
}
static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
@@ -451,7 +429,6 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina);
tcg_gen_sub_i32(out, inb, ina);
tcg_gen_deposit_i32(out, out, lt, 31, 1);
- tcg_temp_free_i32(lt);
}
DO_TYPEA(cmp, false, gen_cmp)
@@ -492,12 +469,12 @@ DO_TYPEA0_CFG(fsqrt, use_fpu >= 2, true, gen_fsqrt)
/* Does not use ENV_WRAPPER3, because arguments are swapped as well. */
static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
- gen_helper_divs(out, cpu_env, inb, ina);
+ gen_helper_divs(out, tcg_env, inb, ina);
}
static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
- gen_helper_divu(out, cpu_env, inb, ina);
+ gen_helper_divu(out, tcg_env, inb, ina);
}
DO_TYPEA_CFG(idiv, use_div, true, gen_idiv)
@@ -518,21 +495,18 @@ static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_muls2_i32(tmp, out, ina, inb);
- tcg_temp_free_i32(tmp);
}
static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_mulu2_i32(tmp, out, ina, inb);
- tcg_temp_free_i32(tmp);
}
static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_mulsu2_i32(tmp, out, ina, inb);
- tcg_temp_free_i32(tmp);
}
DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32)
@@ -568,15 +542,12 @@ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
/* Input and output carry. */
static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_not_i32(tmp, ina);
tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero);
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
-
- tcg_temp_free_i32(zero);
- tcg_temp_free_i32(tmp);
}
/* No input or output carry. */
@@ -593,8 +564,6 @@ static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
tcg_gen_not_i32(nota, ina);
tcg_gen_add_i32(out, inb, nota);
tcg_gen_add_i32(out, out, cpu_msr_c);
-
- tcg_temp_free_i32(nota);
}
DO_TYPEA(rsub, true, gen_rsub)
@@ -623,8 +592,6 @@ static void gen_src(TCGv_i32 out, TCGv_i32 ina)
tcg_gen_mov_i32(tmp, cpu_msr_c);
tcg_gen_andi_i32(cpu_msr_c, ina, 1);
tcg_gen_extract2_i32(out, ina, tmp, 1);
-
- tcg_temp_free_i32(tmp);
}
static void gen_srl(TCGv_i32 out, TCGv_i32 ina)
@@ -664,7 +631,6 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
tcg_gen_extu_i32_tl(ret, tmp);
- tcg_temp_free_i32(tmp);
} else if (ra) {
tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
} else if (rb) {
@@ -674,7 +640,7 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
}
if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
- gen_helper_stackprot(cpu_env, ret);
+ gen_helper_stackprot(tcg_env, ret);
}
return ret;
}
@@ -688,13 +654,12 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
tcg_gen_extu_i32_tl(ret, tmp);
- tcg_temp_free_i32(tmp);
} else {
tcg_gen_movi_tl(ret, (uint32_t)imm);
}
if (ra == 1 && dc->cfg->stackprot) {
- gen_helper_stackprot(cpu_env, ret);
+ gen_helper_stackprot(tcg_env, ret);
}
return ret;
}
@@ -727,18 +692,20 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
}
#endif
+#ifndef CONFIG_USER_ONLY
static void record_unaligned_ess(DisasContext *dc, int rd,
MemOp size, bool store)
{
- uint32_t iflags = tcg_get_insn_start_param(dc->insn_start, 1);
+ uint32_t iflags = tcg_get_insn_start_param(dc->base.insn_start, 1);
iflags |= ESR_ESS_FLAG;
iflags |= rd << 5;
iflags |= store * ESR_S;
iflags |= (size == MO_32) * ESR_W;
- tcg_set_insn_start_param(dc->insn_start, 1, iflags);
+ tcg_set_insn_start_param(dc->base.insn_start, 1, iflags);
}
+#endif
static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
int mem_index, bool rev)
@@ -760,16 +727,21 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
}
}
+ /*
+ * For system mode, enforce alignment if the cpu configuration
+ * requires it. For user-mode, the Linux kernel will have fixed up
+ * any unaligned access, so emulate that by *not* setting MO_ALIGN.
+ */
+#ifndef CONFIG_USER_ONLY
if (size > MO_8 &&
(dc->tb_flags & MSR_EE) &&
dc->cfg->unaligned_exceptions) {
record_unaligned_ess(dc, rd, size, false);
mop |= MO_ALIGN;
}
+#endif
tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop);
-
- tcg_temp_free(addr);
return true;
}
@@ -875,7 +847,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
tcg_gen_mov_tl(cpu_res_addr, addr);
- tcg_temp_free(addr);
if (arg->rd) {
tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
@@ -906,16 +877,21 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
}
}
+ /*
+ * For system mode, enforce alignment if the cpu configuration
+ * requires it. For user-mode, the Linux kernel will have fixed up
+ * any unaligned access, so emulate that by *not* setting MO_ALIGN.
+ */
+#ifndef CONFIG_USER_ONLY
if (size > MO_8 &&
(dc->tb_flags & MSR_EE) &&
dc->cfg->unaligned_exceptions) {
record_unaligned_ess(dc, rd, size, true);
mop |= MO_ALIGN;
}
+#endif
tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);
-
- tcg_temp_free(addr);
return true;
}
@@ -1029,7 +1005,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* In either case, addr is no longer needed.
*/
tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
- tcg_temp_free(addr);
/*
* Compare the value loaded during lwx with current contents of
@@ -1042,7 +1017,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
dc->mem_index, MO_TEUL);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
- tcg_temp_free_i32(tval);
/* Success */
tcg_gen_movi_i32(cpu_msr_c, 0);
@@ -1139,13 +1113,11 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm,
}
/* Compute the final destination into btarget. */
- zero = tcg_const_i32(0);
- next = tcg_const_i32(dc->base.pc_next + (delay + 1) * 4);
+ zero = tcg_constant_i32(0);
+ next = tcg_constant_i32(dc->base.pc_next + (delay + 1) * 4);
tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget,
reg_for_read(dc, ra), zero,
cpu_btarget, next);
- tcg_temp_free_i32(zero);
- tcg_temp_free_i32(next);
return true;
}
@@ -1250,8 +1222,6 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
/* Sleep. */
if (mbar_imm & 16) {
- TCGv_i32 tmp_1;
-
if (trap_userspace(dc, true)) {
/* Sleep is a privileged instruction. */
return true;
@@ -1259,11 +1229,9 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
t_sync_flags(dc);
- tmp_1 = tcg_const_i32(1);
- tcg_gen_st_i32(tmp_1, cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(MicroBlazeCPU, env)
+offsetof(CPUState, halted));
- tcg_temp_free_i32(tmp_1);
tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
@@ -1334,7 +1302,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d)
t = tcg_temp_new_i32();
tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC);
tcg_gen_or_i32(d, cpu_msr, t);
- tcg_temp_free_i32(t);
}
static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
@@ -1411,13 +1378,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR));
break;
case SR_FSR:
- tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr));
+ tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, fsr));
break;
case 0x800:
- tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr));
+ tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, slr));
break;
case 0x802:
- tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr));
+ tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, shr));
break;
case 0x1000: /* PID */
@@ -1427,12 +1394,10 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
case 0x1004: /* TLBHI */
case 0x1005: /* TLBSX */
{
- TCGv_i32 tmp_ext = tcg_const_i32(arg->e);
- TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
+ TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
+ TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);
- gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src);
- tcg_temp_free_i32(tmp_reg);
- tcg_temp_free_i32(tmp_ext);
+ gen_helper_mmu_write(tcg_env, tmp_ext, tmp_reg, src);
}
break;
@@ -1454,9 +1419,8 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
case SR_EAR:
{
TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
+ tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear));
tcg_gen_extrh_i64_i32(dest, t64);
- tcg_temp_free_i64(t64);
}
return true;
#ifndef CONFIG_USER_ONLY
@@ -1485,28 +1449,27 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
case SR_EAR:
{
TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
+ tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear));
tcg_gen_extrl_i64_i32(dest, t64);
- tcg_temp_free_i64(t64);
}
break;
case SR_ESR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, esr));
break;
case SR_FSR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, fsr));
break;
case SR_BTR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, edr));
break;
case 0x800:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, slr));
break;
case 0x802:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, shr));
break;
#ifndef CONFIG_USER_ONLY
@@ -1517,18 +1480,16 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
case 0x1004: /* TLBHI */
case 0x1005: /* TLBSX */
{
- TCGv_i32 tmp_ext = tcg_const_i32(arg->e);
- TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
+ TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
+ TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);
- gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg);
- tcg_temp_free_i32(tmp_reg);
- tcg_temp_free_i32(tmp_ext);
+ gen_helper_mmu_read(dest, tcg_env, tmp_ext, tmp_reg);
}
break;
#endif
case 0x2000 ... 0x200c:
- tcg_gen_ld_i32(dest, cpu_env,
+ tcg_gen_ld_i32(dest, tcg_env,
offsetof(MicroBlazeCPU, cfg.pvr_regs[arg->rs - 0x2000])
- offsetof(MicroBlazeCPU, env));
break;
@@ -1548,8 +1509,6 @@ static void do_rti(DisasContext *dc)
tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM);
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
-
- tcg_temp_free_i32(tmp);
}
static void do_rtb(DisasContext *dc)
@@ -1560,8 +1519,6 @@ static void do_rtb(DisasContext *dc)
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP));
tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
-
- tcg_temp_free_i32(tmp);
}
static void do_rte(DisasContext *dc)
@@ -1573,8 +1530,6 @@ static void do_rte(DisasContext *dc)
tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
-
- tcg_temp_free_i32(tmp);
}
/* Insns connected to FSL or AXI stream attached devices. */
@@ -1593,10 +1548,8 @@ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl)
tcg_gen_movi_i32(t_id, imm);
}
- t_ctrl = tcg_const_i32(ctrl);
+ t_ctrl = tcg_constant_i32(ctrl);
gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl);
- tcg_temp_free_i32(t_id);
- tcg_temp_free_i32(t_ctrl);
return true;
}
@@ -1625,10 +1578,8 @@ static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl)
tcg_gen_movi_i32(t_id, imm);
}
- t_ctrl = tcg_const_i32(ctrl);
+ t_ctrl = tcg_constant_i32(ctrl);
gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra));
- tcg_temp_free_i32(t_id);
- tcg_temp_free_i32(t_ctrl);
return true;
}
@@ -1653,7 +1604,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
dc->ext_imm = dc->base.tb->cs_base;
dc->r0 = NULL;
dc->r0_set = false;
- dc->mem_index = cpu_mmu_index(&cpu->env, false);
+ dc->mem_index = cpu_mmu_index(cs, false);
dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER;
dc->jmp_dest = -1;
@@ -1670,13 +1621,11 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)
DisasContext *dc = container_of(dcb, DisasContext, base);
tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);
- dc->insn_start = tcg_last_op();
}
static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
- CPUMBState *env = cs->env_ptr;
uint32_t ir;
/* TODO: This should raise an exception, not terminate qemu. */
@@ -1687,13 +1636,12 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
dc->tb_flags_to_set = 0;
- ir = cpu_ldl_code(env, dc->base.pc_next);
+ ir = cpu_ldl_code(cpu_env(cs), dc->base.pc_next);
if (!decode(dc, ir)) {
trap_illegal(dc, true);
}
if (dc->r0) {
- tcg_temp_free_i32(dc->r0);
dc->r0 = NULL;
dc->r0_set = false;
}
@@ -1779,7 +1727,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
break;
case DISAS_JUMP:
- if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
+ if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
/* Direct jump. */
tcg_gen_discard_i32(cpu_btarget);
@@ -1804,15 +1752,10 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
return;
}
- /* Indirect jump (or direct jump w/ singlestep) */
+ /* Indirect jump (or direct jump w/ goto_tb disabled) */
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
tcg_gen_discard_i32(cpu_btarget);
-
- if (unlikely(cs->singlestep_enabled)) {
- gen_raise_exception(dc, EXCP_DEBUG);
- } else {
- tcg_gen_lookup_and_goto_ptr();
- }
+ tcg_gen_lookup_and_goto_ptr();
return;
default:
@@ -1827,10 +1770,11 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
}
}
-static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs)
+static void mb_tr_disas_log(const DisasContextBase *dcb,
+ CPUState *cs, FILE *logfile)
{
- qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first));
- log_target_disas(cs, dcb->pc_first, dcb->tb->size);
+ fprintf(logfile, "IN: %s\n", lookup_symbol(dcb->pc_first));
+ target_disas(logfile, cs, dcb->pc_first, dcb->tb->size);
}
static const TranslatorOps mb_tr_ops = {
@@ -1842,16 +1786,16 @@ static const TranslatorOps mb_tr_ops = {
.disas_log = mb_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
+ vaddr pc, void *host_pc)
{
DisasContext dc;
- translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns);
+ translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);
}
void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- CPUMBState *env = &cpu->env;
+ CPUMBState *env = cpu_env(cs);
uint32_t iflags;
int i;
@@ -1932,16 +1876,9 @@ void mb_tcg_init(void)
for (int i = 0; i < ARRAY_SIZE(i32s); ++i) {
*i32s[i].var =
- tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name);
+ tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
}
cpu_res_addr =
- tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr");
-}
-
-void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
- env->iflags = data[1];
+ tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr");
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-25 15:14:36 +0000