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-rw-r--r--target/arm/cpu.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a98c45b1ff..f9da672be5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3388,6 +3388,12 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
+static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports double precision floating point */
+ return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so