diff options
Diffstat (limited to 'target/alpha/helper.c')
| -rw-r--r-- | target/alpha/helper.c | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 5fe9c87912..2134ee1e9d 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -29,12 +29,12 @@ #define CONVERT_BIT(X, SRC, DST) \ (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) -uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env) +uint64_t cpu_alpha_load_fpcr(CPUAlphaState *env) { return (uint64_t)env->fpcr << 32; } -void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val) +void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val) { uint32_t fpcr = val >> 32; uint32_t t = 0; @@ -67,6 +67,22 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val) env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ); env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0; + +#ifdef CONFIG_USER_ONLY + /* + * Override some of these bits with the contents of ENV->SWCR. + * In system mode, some of these would trap to the kernel, at + * which point the kernel's handler would emulate and apply + * the software exception mask. + */ + if (env->swcr & SWCR_MAP_DMZ) { + env->fp_status.flush_inputs_to_zero = 1; + } + if (env->swcr & SWCR_MAP_UMZ) { + env->fp_status.flush_to_zero = 1; + } + env->fpcr_exc_enable &= ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32); +#endif } uint64_t helper_load_fpcr(CPUAlphaState *env) @@ -435,32 +451,33 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - static const char *linux_reg_names[] = { - "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ", - "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ", - "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ", - "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero", + static const char linux_reg_names[31][4] = { + "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", + "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", + "t10", "t11", "ra", "t12", "at", "gp", "sp" }; AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; int i; - qemu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", + qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8)); for (i = 0; i < 31; i++) { - qemu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i, + qemu_fprintf(f, "%-8s" TARGET_FMT_lx "%c", linux_reg_names[i], cpu_alpha_load_gr(env, i), (i % 3) == 2 ? '\n' : ' '); } - qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n", + qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n", env->lock_addr, env->lock_value); if (flags & CPU_DUMP_FPU) { for (i = 0; i < 31; i++) { - qemu_fprintf(f, "FIR%02d %016" PRIx64 "%c", i, env->fir[i], + qemu_fprintf(f, "f%-7d%016" PRIx64 "%c", i, env->fir[i], (i % 3) == 2 ? '\n' : ' '); } + qemu_fprintf(f, "fpcr %016" PRIx64 "\n", cpu_alpha_load_fpcr(env)); } qemu_fprintf(f, "\n"); } |