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Diffstat (limited to 'target-arm/helper.c')
-rw-r--r--target-arm/helper.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0a9c6fc5e2..1fda6be295 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -342,7 +342,9 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
- tlb_flush_page(env, value & TARGET_PAGE_MASK);
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -356,7 +358,9 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
- tlb_flush_page(env, value & TARGET_PAGE_MASK);
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
static const ARMCPRegInfo cp_reginfo[] = {
@@ -1686,16 +1690,18 @@ static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by VA (AArch64 version) */
+ ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t pageaddr = value << 12;
- tlb_flush_page(env, pageaddr);
+ tlb_flush_page(CPU(cpu), pageaddr);
}
static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by VA, all ASIDs (AArch64 version) */
+ ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t pageaddr = value << 12;
- tlb_flush_page(env, pageaddr);
+ tlb_flush_page(CPU(cpu), pageaddr);
}
static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,