diff options
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 136 |
1 files changed, 57 insertions, 79 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index b6e10fd98c..346c61c089 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -485,6 +485,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = { */ { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, .access = PL1_W, .type = ARM_CP_WFI }, + /* L1 cache lockdown. Not architectural in v6 and earlier but in practice + * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and + * OMAPCP will override this space. + */ + { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), + .resetvalue = 0 }, + { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), + .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -889,6 +899,9 @@ static const ARMCPRegInfo omap_cp_reginfo[] = { { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .writefn = omap_cachemaint_write }, + { .name = "C9", .cp = 15, .crn = 9, + .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -949,6 +962,33 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo cortexa8_cp_reginfo[] = { + { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + /* Linux wants the number of processors from here. + * Might as well set the interrupt-controller bit too. + */ + *value = ((smp_cpus - 1) << 24) | (1 << 23); + return 0; +} + +static const ARMCPRegInfo cortexa15_cp_reginfo[] = { + { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, + .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, + .writefn = arm_cp_write_ignore, }, + { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { /* RAZ/WI the whole crn=15 space, when we don't have a more specific * implementation of this implementation-defined space. @@ -986,6 +1026,14 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo strongarm_cp_reginfo[] = { + /* Ignore ReadBuffer accesses */ + { .name = "C9_READBUFFER", .cp = 15, .crn = 9, + .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -1043,6 +1091,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_OMAPCP)) { define_arm_cp_regs(env, omap_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_STRONGARM)) { + define_arm_cp_regs(env, strongarm_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_XSCALE)) { define_arm_cp_regs(env, xscale_cp_reginfo); } @@ -1055,9 +1106,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) case ARM_CPUID_ARM1026: define_arm_cp_regs(env, arm1026_cp_reginfo); break; + case ARM_CPUID_CORTEXA8: + define_arm_cp_regs(env, cortexa8_cp_reginfo); + break; case ARM_CPUID_CORTEXA9: define_arm_cp_regs(env, cortexa9_cp_reginfo); break; + case ARM_CPUID_CORTEXA15: + define_arm_cp_regs(env, cortexa15_cp_reginfo); + break; default: break; } @@ -2158,40 +2215,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) break; case 4: /* Reserved. */ goto bad_reg; - case 9: - if (arm_feature(env, ARM_FEATURE_OMAPCP)) - break; - if (arm_feature(env, ARM_FEATURE_STRONGARM)) - break; /* Ignore ReadBuffer access */ - switch (crm) { - case 0: /* Cache lockdown. */ - switch (op1) { - case 0: /* L1 cache. */ - switch (op2) { - case 0: - env->cp15.c9_data = val; - break; - case 1: - env->cp15.c9_insn = val; - break; - default: - goto bad_reg; - } - break; - case 1: /* L2 cache. */ - /* Ignore writes to L2 lockdown/auxiliary registers. */ - break; - default: - goto bad_reg; - } - break; - case 1: /* TCM memory region registers. */ - /* Not implemented. */ - goto bad_reg; - default: - goto bad_reg; - } - break; case 12: /* Reserved. */ goto bad_reg; } @@ -2331,51 +2354,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) } case 4: /* Reserved. */ goto bad_reg; - case 9: - switch (crm) { - case 0: /* Cache lockdown */ - switch (op1) { - case 0: /* L1 cache. */ - if (arm_feature(env, ARM_FEATURE_OMAPCP)) { - return 0; - } - switch (op2) { - case 0: - return env->cp15.c9_data; - case 1: - return env->cp15.c9_insn; - default: - goto bad_reg; - } - case 1: /* L2 cache */ - /* L2 Lockdown and Auxiliary control. */ - switch (op2) { - case 0: - /* L2 cache lockdown (A8 only) */ - return 0; - case 2: - /* L2 cache auxiliary control (A8) or control (A15) */ - if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) { - /* Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((smp_cpus - 1) << 24) | (1 << 23); - } - return 0; - case 3: - /* L2 cache extended control (A15) */ - return 0; - default: - goto bad_reg; - } - default: - goto bad_reg; - } - break; - default: - goto bad_reg; - } - break; case 11: /* TCM DMA control. */ case 12: /* Reserved. */ goto bad_reg; |