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-rw-r--r--hw/ppc/sam460ex.c437
1 files changed, 191 insertions, 246 deletions
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 84ea592749..d42b677898 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -2,7 +2,7 @@
* QEMU aCube Sam460ex board emulation
*
* Copyright (c) 2012 François Revol
- * Copyright (c) 2016-2018 BALATON Zoltan
+ * Copyright (c) 2016-2019 BALATON Zoltan
*
* This file is derived from hw/ppc440_bamboo.c,
* the copyright for that material belongs to the original owners.
@@ -13,10 +13,9 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
-#include "qemu-common.h"
+#include "qemu/datadir.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
-#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
@@ -24,19 +23,21 @@
#include "sysemu/block-backend.h"
#include "hw/loader.h"
#include "elf.h"
-#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "ppc440.h"
-#include "ppc405.h"
+#include "hw/pci-host/ppc4xx.h"
#include "hw/block/flash.h"
#include "sysemu/sysemu.h"
-#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "hw/i2c/ppc4xx_i2c.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_eeprom.h"
+#include "hw/ide/pci.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/ppc/fdt.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/ppc-uic.h"
#include <libfdt.h>
@@ -46,6 +47,9 @@
/* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
if=updater/updater-460 of=u-boot-sam460-20100605.bin */
+#define PCIE0_DCRN_BASE 0x100
+#define PCIE1_DCRN_BASE 0x120
+
/* from Sam460 U-Boot include/configs/Sam460ex.h */
#define FLASH_BASE 0xfff00000
#define FLASH_BASE_H 0x4
@@ -74,12 +78,6 @@
#define OPB_FREQ 115000000
#define EBC_FREQ 115000000
#define UART_FREQ 11059200
-#define SDRAM_NR_BANKS 4
-
-/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
-static const unsigned int ppc460ex_sdram_bank_sizes[] = {
- 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 0
-};
struct boot_info {
uint32_t dt_base;
@@ -87,175 +85,55 @@ struct boot_info {
uint32_t entry;
};
-/*****************************************************************************/
-/* SPD eeprom content from mips_malta.c */
-
-struct _eeprom24c0x_t {
- uint8_t tick;
- uint8_t address;
- uint8_t command;
- uint8_t ack;
- uint8_t scl;
- uint8_t sda;
- uint8_t data;
- uint8_t contents[256];
-};
-
-typedef struct _eeprom24c0x_t eeprom24c0x_t;
-
-static eeprom24c0x_t spd_eeprom = {
- .contents = {
- /* 00000000: */ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
- /* 00000008: */ 0x04, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
- /* 00000010: */ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
- /* 00000018: */ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
- /* 00000020: */ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
- /* 00000028: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000030: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000038: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
- /* 00000040: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000048: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000050: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000058: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000060: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000068: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000070: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 00000078: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
- },
-};
-
-static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
-{
- enum { SDR = 0x4, DDR1 = 0x7, DDR2 = 0x8 } type;
- uint8_t *spd = spd_eeprom.contents;
- uint8_t nbanks = 0;
- uint16_t density = 0;
- int i;
-
- /* work in terms of MB */
- ram_size /= MiB;
-
- while ((ram_size >= 4) && (nbanks <= 2)) {
- int sz_log2 = MIN(31 - clz32(ram_size), 14);
- nbanks++;
- density |= 1 << (sz_log2 - 2);
- ram_size -= 1 << sz_log2;
- }
-
- /* split to 2 banks if possible */
- if ((nbanks == 1) && (density > 1)) {
- nbanks++;
- density >>= 1;
- }
-
- if (density & 0xff00) {
- density = (density & 0xe0) | ((density >> 8) & 0x1f);
- type = DDR2;
- } else if (!(density & 0x1f)) {
- type = DDR2;
- } else {
- type = SDR;
- }
-
- if (ram_size) {
- warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
- " of SDRAM", ram_size);
- }
-
- /* fill in SPD memory information */
- spd[2] = type;
- spd[5] = nbanks;
- spd[31] = density;
-
- /* XXX: this is totally random */
- spd[9] = 0x10; /* CAS tcyc */
- spd[18] = 0x20; /* CAS bit */
- spd[23] = 0x10; /* CAS tcyc */
- spd[25] = 0x10; /* CAS tcyc */
-
- /* checksum */
- spd[63] = 0;
- for (i = 0; i < 63; i++) {
- spd[63] += spd[i];
- }
-
- /* copy for SMBUS */
- memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
-}
-
-static void generate_eeprom_serial(uint8_t *eeprom)
-{
- int i, pos = 0;
- uint8_t mac[6] = { 0x00 };
- uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
-
- /* version */
- eeprom[pos++] = 0x01;
-
- /* count */
- eeprom[pos++] = 0x02;
-
- /* MAC address */
- eeprom[pos++] = 0x01; /* MAC */
- eeprom[pos++] = 0x06; /* length */
- memcpy(&eeprom[pos], mac, sizeof(mac));
- pos += sizeof(mac);
-
- /* serial number */
- eeprom[pos++] = 0x02; /* serial */
- eeprom[pos++] = 0x05; /* length */
- memcpy(&eeprom[pos], sn, sizeof(sn));
- pos += sizeof(sn);
-
- /* checksum */
- eeprom[pos] = 0;
- for (i = 0; i < pos; i++) {
- eeprom[pos] += eeprom[i];
- }
-}
-
-/*****************************************************************************/
-
static int sam460ex_load_uboot(void)
{
+ /*
+ * This first creates 1MiB of flash memory mapped at the end of
+ * the 32-bit address space (0xFFF00000..0xFFFFFFFF).
+ *
+ * If_PFLASH unit 0 is defined, the flash memory is initialized
+ * from that block backend.
+ *
+ * Else, it's initialized to zero. And then 512KiB of ROM get
+ * mapped on top of its second half (0xFFF80000..0xFFFFFFFF),
+ * initialized from u-boot-sam460-20100605.bin.
+ *
+ * This doesn't smell right.
+ *
+ * The physical hardware appears to have 512KiB flash memory.
+ *
+ * TODO Figure out what we really need here, and clean this up.
+ */
+
DriveInfo *dinfo;
- BlockBackend *blk = NULL;
- hwaddr base = FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32);
- long bios_size = FLASH_SIZE;
- int fl_sectors;
dinfo = drive_get(IF_PFLASH, 0, 0);
- if (dinfo) {
- blk = blk_by_legacy_dinfo(dinfo);
- bios_size = blk_getlength(blk);
- }
- fl_sectors = (bios_size + 65535) >> 16;
-
- if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size,
- blk, 64 * KiB, fl_sectors,
- 1, 0x89, 0x18, 0x0000, 0x0, 1)) {
+ if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32),
+ "sam460ex.flash", FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) {
error_report("Error registering flash memory");
/* XXX: return an error instead? */
exit(1);
}
- if (!blk) {
+ if (!dinfo) {
/*error_report("No flash image given with the 'pflash' parameter,"
" using default u-boot image");*/
- base = UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32);
- rom_add_file_fixed(UBOOT_FILENAME, base, -1);
+ rom_add_file_fixed(UBOOT_FILENAME,
+ UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32),
+ -1);
}
return 0;
}
-static int sam460ex_load_device_tree(hwaddr addr,
- uint32_t ramsize,
+static int sam460ex_load_device_tree(MachineState *machine,
+ hwaddr addr,
hwaddr initrd_base,
- hwaddr initrd_size,
- const char *kernel_cmdline)
+ hwaddr initrd_size)
{
- uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
+ uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) };
char *filename;
int fdt_size;
void *fdt;
@@ -289,7 +167,8 @@ static int sam460ex_load_device_tree(hwaddr addr,
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
(initrd_base + initrd_size));
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
/* Copy data from the host device tree into the guest. Since the guest can
* directly access the timebase without host involvement, we must expose
@@ -326,7 +205,9 @@ static int sam460ex_load_device_tree(hwaddr addr,
EBC_FREQ);
rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
- g_free(fdt);
+
+ /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+ machine->fdt = fdt;
return fdt_size;
}
@@ -390,27 +271,21 @@ static void main_cpu_reset(void *opaque)
static void sam460ex_init(MachineState *machine)
{
- MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *isa = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
- hwaddr ram_bases[SDRAM_NR_BANKS];
- hwaddr ram_sizes[SDRAM_NR_BANKS];
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
- qemu_irq *irqs, *uic[4];
+ DeviceState *uic[4];
+ int i;
PCIBus *pci_bus;
+ USBBus *usb_bus;
PowerPCCPU *cpu;
CPUPPCState *env;
- PPC4xxI2CState *i2c[2];
+ I2CBus *i2c;
hwaddr entry = UBOOT_ENTRY;
- hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
target_long initrd_size = 0;
DeviceState *dev;
SysBusDevice *sbdev;
- int success;
- int i;
struct boot_info *boot_info;
- const size_t smbus_eeprom_size = 8 * 256;
- uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
+ uint8_t *spd_data;
+ int success;
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
@@ -427,50 +302,85 @@ static void sam460ex_init(MachineState *machine)
ppc_dcr_init(env, NULL, NULL);
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ dev = qdev_new(TYPE_PPC4xx_PLB);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* interrupt controllers */
- irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
- irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
- irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
- uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
- uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
- uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
- uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
+ for (i = 0; i < ARRAY_SIZE(uic); i++) {
+ /*
+ * UICs 1, 2 and 3 are cascaded through UIC 0.
+ * input_ints[n] is the interrupt number on UIC 0 which
+ * the INT output of UIC n is connected to. The CINT output
+ * of UIC n connects to input_ints[n] + 1.
+ * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's
+ * INT and CINT outputs are connected to the CPU.
+ */
+ const int input_ints[] = { -1, 30, 10, 16 };
+
+ uic[i] = qdev_new(TYPE_PPC_UIC);
+ qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal);
+ object_unref(OBJECT(uic[i]));
+
+ sbdev = SYS_BUS_DEVICE(uic[i]);
+ if (i == 0) {
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
+ qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
+ qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
+ } else {
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
+ qdev_get_gpio_in(uic[0], input_ints[i]));
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
+ qdev_get_gpio_in(uic[0], input_ints[i] + 1));
+ }
+ }
/* SDRAM controller */
- memset(ram_bases, 0, sizeof(ram_bases));
- memset(ram_sizes, 0, sizeof(ram_sizes));
- /* put all RAM on first bank because board has one slot
- * and firmware only checks that */
- machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
- ram_memories, ram_bases, ram_sizes,
- ppc460ex_sdram_bank_sizes);
-
- /* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
-
- /* generate SPD EEPROM data */
- for (i = 0; i < SDRAM_NR_BANKS; i++) {
- generate_eeprom_spd(&smbus_eeprom_buf[i * 256], ram_sizes[i]);
+ /* The SoC could also handle 4 GiB but firmware does not work with that. */
+ if (machine->ram_size > 2 * GiB) {
+ error_report("Memory over 2 GiB is not supported");
+ exit(1);
}
- generate_eeprom_serial(&smbus_eeprom_buf[4 * 256]);
- generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
-
- /* IIC controllers */
- dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
- i2c[0] = PPC4xx_I2C(dev);
- object_property_set_bool(OBJECT(dev), true, "realized", NULL);
- smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size);
- g_free(smbus_eeprom_buf);
- i2c_create_slave(i2c[0]->bus, "m41t80", 0x68);
-
- dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
- i2c[1] = PPC4xx_I2C(dev);
+ /* Firmware needs at least 64 MiB */
+ if (machine->ram_size < 64 * MiB) {
+ error_report("Memory below 64 MiB is not supported");
+ exit(1);
+ }
+ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
+ object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
+ /*
+ * Put all RAM on first bank because board has one slot
+ * and firmware only checks that
+ */
+ object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
+ /* FIXME: does 460EX have ECC interrupts? */
+ /* Enable SDRAM memory regions as we may boot without firmware */
+ ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev));
+
+ /* IIC controllers and devices */
+ dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
+ qdev_get_gpio_in(uic[0], 2));
+ i2c = PPC4xx_I2C(dev)->bus;
+ /* SPD EEPROM on RAM module */
+ spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2,
+ machine->ram_size);
+ spd_data[20] = 4; /* SO-DIMM module */
+ smbus_eeprom_init_one(i2c, 0x50, spd_data);
+ /* RTC */
+ i2c_slave_create_simple(i2c, "m41t80", 0x68);
+
+ dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800,
+ qdev_get_gpio_in(uic[0], 3));
/* External bus controller */
- ppc405_ebc_init(env);
+ dev = qdev_new(TYPE_PPC4xx_EBC);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* CPR */
ppc4xx_cpr_init(env);
@@ -482,7 +392,15 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdr_init(env);
/* MAL */
- ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
+ dev = qdev_new(TYPE_PPC4xx_MAL);
+ qdev_prop_set_uint8(dev, "txc-num", 4);
+ qdev_prop_set_uint8(dev, "rxc-num", 16);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
+ sbdev = SYS_BUS_DEVICE(dev);
+ for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) {
+ sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i));
+ }
/* DMA */
ppc4xx_dma_init(env, 0x200);
@@ -492,51 +410,76 @@ static void sam460ex_init(MachineState *machine)
/* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
&error_abort);
- memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
+ memory_region_add_subregion(get_system_memory(), 0x400000000LL,
+ l2cache_ram);
/* USB */
- sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
- dev = qdev_create(NULL, "sysbus-ohci");
+ sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400,
+ qdev_get_gpio_in(uic[2], 29));
+ dev = qdev_new("sysbus-ohci");
qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
qdev_prop_set_uint32(dev, "num-ports", 6);
- qdev_init_nofail(dev);
sbdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbdev, &error_fatal);
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
- sysbus_connect_irq(sbdev, 0, uic[2][30]);
- usb_create_simple(usb_bus_find(-1), "usb-kbd");
- usb_create_simple(usb_bus_find(-1), "usb-mouse");
+ sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30));
+ usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
+ &error_abort));
+ usb_create_simple(usb_bus, "usb-kbd");
+ usb_create_simple(usb_bus, "usb-mouse");
+
+ /* PCIe buses */
+ dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
+ qdev_prop_set_int32(dev, "busnum", 0);
+ qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE);
+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
+ qdev_prop_set_int32(dev, "busnum", 1);
+ qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE);
+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* PCI bus */
- ppc460ex_pcie_init(env);
/* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
- dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0]);
- pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
- if (!pci_bus) {
- error_report("couldn't create PCI controller!");
- exit(1);
- }
- memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
- 0, 0x10000);
- memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
+ dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec00000,
+ qdev_get_gpio_in(uic[1], 0));
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc08000000);
+ pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
/* PCI devices */
pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
- /* SoC has a single SATA port but we don't emulate that yet
+ /*
+ * SoC has a single SATA port but we don't emulate that
* However, firmware and usual clients have driver for SiI311x
- * so add one for convenience by default */
+ * PCI SATA card so add one for convenience by default
+ */
if (defaults_enabled()) {
- pci_create_simple(pci_bus, -1, "sii3112");
+ PCIIDEState *s = PCI_IDE(pci_create_simple(pci_bus, -1, "sii3112"));
+ DriveInfo *di;
+
+ di = drive_get_by_index(IF_IDE, 0);
+ if (di) {
+ ide_bus_create_drive(&s->bus[0], 0, di);
+ }
+ /* Use index 2 only if 1 does not exist, this allows -cdrom */
+ di = drive_get_by_index(IF_IDE, 1) ?: drive_get_by_index(IF_IDE, 2);
+ if (di) {
+ ide_bus_create_drive(&s->bus[1], 0, di);
+ }
}
- /* SoC has 4 UARTs
- * but board has only one wired and two are present in fdt */
+ /* SoC has 4 UARTs but board has only one wired and two described in fdt */
if (serial_hd(0) != NULL) {
- serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
+ serial_mm_init(get_system_memory(), 0x4ef600300, 0,
+ qdev_get_gpio_in(uic[1], 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
- serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
+ serial_mm_init(get_system_memory(), 0x4ef600400, 0,
+ qdev_get_gpio_in(uic[0], 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
@@ -552,15 +495,16 @@ static void sam460ex_init(MachineState *machine)
/* Load kernel. */
if (machine->kernel_filename) {
+ hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
NULL, NULL, NULL);
if (success < 0) {
- uint64_t elf_entry, elf_lowaddr;
+ uint64_t elf_entry;
- success = load_elf(machine->kernel_filename, NULL, NULL, &elf_entry,
- &elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0);
+ success = load_elf(machine->kernel_filename, NULL, NULL, NULL,
+ &elf_entry, NULL, NULL, NULL,
+ 1, PPC_ELF_MACHINE, 0, 0);
entry = elf_entry;
- loadaddr = elf_lowaddr;
}
/* XXX try again as binary */
if (success < 0) {
@@ -586,9 +530,8 @@ static void sam460ex_init(MachineState *machine)
if (machine->kernel_filename) {
int dt_size;
- dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
- RAMDISK_ADDR, initrd_size,
- machine->kernel_cmdline);
+ dt_size = sam460ex_load_device_tree(machine, FDT_ADDR,
+ RAMDISK_ADDR, initrd_size);
boot_info->dt_base = FDT_ADDR;
boot_info->dt_size = dt_size;
@@ -601,8 +544,10 @@ static void sam460ex_machine_init(MachineClass *mc)
{
mc->desc = "aCube Sam460ex";
mc->init = sam460ex_init;
+ mc->block_default_type = IF_IDE;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
mc->default_ram_size = 512 * MiB;
+ mc->default_ram_id = "ppc4xx.sdram";
}
DEFINE_MACHINE("sam460ex", sam460ex_machine_init)
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-18 13:28:32 +0000