diff options
Diffstat (limited to 'hw/alpha/typhoon.c')
-rw-r--r-- | hw/alpha/typhoon.c | 122 |
1 files changed, 52 insertions, 70 deletions
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index d74b5b55e1..e8711ae16a 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -7,14 +7,13 @@ */ #include "qemu/osdep.h" +#include "qemu/module.h" #include "qemu/units.h" #include "qapi/error.h" +#include "hw/pci/pci_host.h" #include "cpu.h" -#include "hw/hw.h" -#include "hw/devices.h" -#include "sysemu/sysemu.h" +#include "hw/irq.h" #include "alpha_sys.h" -#include "exec/address-spaces.h" #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost" @@ -49,17 +48,15 @@ typedef struct TyphoonPchip { TyphoonWindow win[4]; } TyphoonPchip; -#define TYPHOON_PCI_HOST_BRIDGE(obj) \ - OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE) +OBJECT_DECLARE_SIMPLE_TYPE(TyphoonState, TYPHOON_PCI_HOST_BRIDGE) -typedef struct TyphoonState { +struct TyphoonState { PCIHostState parent_obj; TyphoonCchip cchip; TyphoonPchip pchip; MemoryRegion dchip_region; - MemoryRegion ram_region; -} TyphoonState; +}; /* Called when one of DRIR or DIM changes. */ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) @@ -75,7 +72,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) } } -static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult cchip_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { CPUState *cpu = current_cpu; TyphoonState *s = opaque; @@ -196,11 +195,11 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cpu_unassigned_access(cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } - return ret; + *data = ret; + return MEMTX_OK; } static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) @@ -209,7 +208,8 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) return 0; } -static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t ret = 0; @@ -294,15 +294,16 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cpu_unassigned_access(current_cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } - return ret; + *data = ret; + return MEMTX_OK; } -static void cchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult cchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t oldval, newval; @@ -446,9 +447,10 @@ static void cchip_write(void *opaque, hwaddr addr, break; default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } static void dchip_write(void *opaque, hwaddr addr, @@ -457,8 +459,9 @@ static void dchip_write(void *opaque, hwaddr addr, /* Skip this. It's all related to DRAM timing and setup. */ } -static void pchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult pchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t oldval; @@ -553,14 +556,15 @@ static void pchip_write(void *opaque, hwaddr addr, break; default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } static const MemoryRegionOps cchip_ops = { - .read = cchip_read, - .write = cchip_write, + .read_with_attrs = cchip_read, + .write_with_attrs = cchip_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 8, @@ -587,8 +591,8 @@ static const MemoryRegionOps dchip_ops = { }; static const MemoryRegionOps pchip_ops = { - .read = pchip_read, - .write = pchip_write, + .read_with_attrs = pchip_read, + .write_with_attrs = pchip_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 8, @@ -657,8 +661,8 @@ static bool window_translate(TyphoonWindow *win, hwaddr addr, pte_addr |= (addr & (wsm | 0xfe000)) >> 10; return pte_translate(pte_addr, ret); } else { - /* Direct-mapped translation. */ - return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret); + /* Direct-mapped translation. */ + return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret); } } @@ -693,7 +697,7 @@ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu, /* Check the fourth window for DAC disable. */ if ((pchip->win[3].wba & 0x80000000000ull) == 0 - && window_translate(&pchip->win[3], addr, &ret)) { + && window_translate(&pchip->win[3], addr, &ret)) { goto success; } } else { @@ -704,7 +708,7 @@ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu, if (pchip->ctl & 0x40) { /* See 10.1.4.4; in particular <39:35> is ignored. */ make_iommu_tlbe(0, 0x007ffffffffull, &ret); - goto success; + goto success; } } @@ -716,8 +720,8 @@ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu, pte_addr = pchip->win[3].tba & 0x7ffc00000ull; pte_addr |= (addr & 0xffffe000u) >> 10; if (pte_translate(pte_addr, &ret)) { - goto success; - } + goto success; + } } } } @@ -734,6 +738,10 @@ static AddressSpace *typhoon_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) return &s->pchip.iommu_as; } +static const PCIIOMMUOps typhoon_iommu_ops = { + .get_address_space = typhoon_pci_dma_iommu, +}; + static void typhoon_set_irq(void *opaque, int irq, int level) { TyphoonState *s = opaque; @@ -810,9 +818,9 @@ static void typhoon_alarm_timer(void *opaque) cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); } -PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, - qemu_irq *p_rtc_irq, - AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq) +PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, + qemu_irq *p_rtc_irq, AlphaCPU *cpus[4], + pci_map_irq_fn sys_map_irq, uint8_t devfn_min) { MemoryRegion *addr_space = get_system_memory(); DeviceState *dev; @@ -821,7 +829,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, PCIBus *b; int i; - dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE); + dev = qdev_new(TYPE_TYPHOON_PCI_HOST_BRIDGE); s = TYPHOON_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); @@ -840,13 +848,12 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, } } + *p_isa_irq = qemu_allocate_irq(typhoon_set_isa_irq, s, 0); *p_rtc_irq = qemu_allocate_irq(typhoon_set_timer_irq, s, 0); /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB, but the address space hole reserved at this point is 8TB. */ - memory_region_allocate_system_memory(&s->ram_region, OBJECT(s), "ram", - ram_size); - memory_region_add_subregion(addr_space, 0, &s->ram_region); + memory_region_add_subregion(addr_space, 0, ram); /* TIGbus, 0x801.0000.0000, 1GB. */ /* ??? The TIGbus is used for delivering interrupts, and access to @@ -884,9 +891,9 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, b = pci_register_root_bus(dev, "pci", typhoon_set_irq, sys_map_irq, s, &s->pchip.reg_mem, &s->pchip.reg_io, - 0, 64, TYPE_PCI_BUS); + devfn_min, 64, TYPE_PCI_BUS); phb->bus = b; - qdev_init_nofail(dev); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* Host memory as seen from the PCI side, via the IOMMU. */ memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu), @@ -894,7 +901,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, "iommu-typhoon", UINT64_MAX); address_space_init(&s->pchip.iommu_as, MEMORY_REGION(&s->pchip.iommu), "pchip0-pci"); - pci_setup_iommu(b, typhoon_pci_dma_iommu, s); + pci_setup_iommu(b, &typhoon_iommu_ops, s); /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, @@ -917,38 +924,13 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB. */ /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */ - /* Init the ISA bus. */ - /* ??? Technically there should be a cy82c693ub pci-isa bridge. */ - { - qemu_irq *isa_irqs; - - *isa_bus = isa_bus_new(NULL, get_system_memory(), &s->pchip.reg_io, - &error_abort); - isa_irqs = i8259_init(*isa_bus, - qemu_allocate_irq(typhoon_set_isa_irq, s, 0)); - isa_bus_irqs(*isa_bus, isa_irqs); - } - return b; } -static int typhoon_pcihost_init(SysBusDevice *dev) -{ - return 0; -} - -static void typhoon_pcihost_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - - k->init = typhoon_pcihost_init; -} - static const TypeInfo typhoon_pcihost_info = { .name = TYPE_TYPHOON_PCI_HOST_BRIDGE, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(TyphoonState), - .class_init = typhoon_pcihost_class_init, }; static void typhoon_iommu_memory_region_class_init(ObjectClass *klass, |