diff options
| author | Stefan Weil <sw@weilnetz.de> | 2012-09-18 22:43:38 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-09-27 21:28:25 +0200 |
| commit | 6673f47da21718d07346b0f3725f0dbf0d6d8e45 (patch) | |
| tree | 0b99abc812e847593fc8c485aacc0eb270a164bc /tci.c | |
| parent | ac05f3492421caeb05809ffa02c6198ede179e43 (diff) | |
tci: Fix for AREG0 free mode
Support for helper functions with 5 arguments was missing
in the code generator and in the interpreter.
There is no need to pass the constant TCG_AREG0 from the
code generator to the interpreter. Remove that code for
the INDEX_op_qemu_st* opcodes.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tci.c')
| -rw-r--r-- | tci.c | 13 |
1 files changed, 9 insertions, 4 deletions
@@ -36,17 +36,19 @@ tcg_abort(); \ } while (0) -#if MAX_OPC_PARAM_IARGS != 4 +#if MAX_OPC_PARAM_IARGS != 5 # error Fix needed, number of supported input arguments changed! #endif #if TCG_TARGET_REG_BITS == 32 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, + tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong); #else typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); + tcg_target_ulong, tcg_target_ulong, + tcg_target_ulong); #endif /* TCI can optionally use a global register variable for env. */ @@ -489,14 +491,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr) tci_read_reg(TCG_REG_R5), tci_read_reg(TCG_REG_R6), tci_read_reg(TCG_REG_R7), - tci_read_reg(TCG_REG_R8)); + tci_read_reg(TCG_REG_R8), + tci_read_reg(TCG_REG_R9), + tci_read_reg(TCG_REG_R10)); tci_write_reg(TCG_REG_R0, tmp64); tci_write_reg(TCG_REG_R1, tmp64 >> 32); #else tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0), tci_read_reg(TCG_REG_R1), tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3)); + tci_read_reg(TCG_REG_R3), + tci_read_reg(TCG_REG_R5)); tci_write_reg(TCG_REG_R0, tmp64); #endif break; |