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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-09 18:50:53 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-09 18:50:53 +0000
commitd42f183c0452a9c769b91e3911566566724983ff (patch)
tree6a6c0ef04844f2a0a6f0542cb7c62554a682c63c /tcg/tcg-opc.h
parenta1f6684d6576df57175c18bfe3fbf23cb61922ab (diff)
downloadqemu-arm-d42f183c0452a9c769b91e3911566566724983ff.tar.gz
Implement TCG rotation ops for x86-64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tcg/tcg-opc.h')
-rw-r--r--tcg/tcg-opc.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 17c4bfba83..9b7b863c06 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -67,10 +67,12 @@ DEF2(divu2_i32, 2, 3, 0, 0)
DEF2(and_i32, 1, 2, 0, 0)
DEF2(or_i32, 1, 2, 0, 0)
DEF2(xor_i32, 1, 2, 0, 0)
-/* shifts */
+/* shifts/rotates */
DEF2(shl_i32, 1, 2, 0, 0)
DEF2(shr_i32, 1, 2, 0, 0)
DEF2(sar_i32, 1, 2, 0, 0)
+DEF2(rotl_i32, 1, 2, 0, 0)
+DEF2(rotr_i32, 1, 2, 0, 0)
DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#if TCG_TARGET_REG_BITS == 32
@@ -120,10 +122,12 @@ DEF2(divu2_i64, 2, 3, 0, 0)
DEF2(and_i64, 1, 2, 0, 0)
DEF2(or_i64, 1, 2, 0, 0)
DEF2(xor_i64, 1, 2, 0, 0)
-/* shifts */
+/* shifts/rotates */
DEF2(shl_i64, 1, 2, 0, 0)
DEF2(shr_i64, 1, 2, 0, 0)
DEF2(sar_i64, 1, 2, 0, 0)
+DEF2(rotl_i64, 1, 2, 0, 0)
+DEF2(rotr_i64, 1, 2, 0, 0)
DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#ifdef TCG_TARGET_HAS_ext8s_i64