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authorThomas Huth <thuth@de.ibm.com>2011-09-09 15:58:37 +1000
committermalc <av1474@comtv.ru>2011-09-09 19:07:06 +0400
commite89720b116131938fe3d4931302f69a28249c934 (patch)
tree27a8992aebbd9c51cdfc6c9ab0e924c636913dd5 /tcg/ppc64
parent07ff2c4475df77e38a31d50ee7f3932631806c15 (diff)
tcg/ppc64: Fix zero extension code generation bug for ppc64 host
The ppc64 code generation backend uses an rldicr (Rotate Left Double Immediate and Clear Right) instruction to implement zero extension of a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However this is wrong - this instruction clears specified low bits of the value, instead of high bits as we require for a zero extension. It should instead use an rldicl (Rotate Left Double Immediate and Clear Left) instruction. Presumably amongst other things, this causes the SLOF firmware image used with -M pseries to not boot on a ppc64 host. It appears this bug was exposed by commit 0bf1dbdcc935dfc220a93cd990e947e90706aec6 (tcg/ppc64: fix 16/32 mixup) which enabled the use of the op_ext32u_i64 operation on the ppc64 backend. Signed-off-by: Thomas Huth <thuth@de.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'tcg/ppc64')
-rw-r--r--tcg/ppc64/tcg-target.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index d831684803..e3c63adc3e 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1560,7 +1560,7 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_ext32u_i64:
- tcg_out_rld (s, RLDICR, args[0], args[1], 0, 32);
+ tcg_out_rld (s, RLDICL, args[0], args[1], 0, 32);
break;
case INDEX_op_setcond_i32: