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authorPeter Maydell <peter.maydell@linaro.org>2018-04-10 14:42:03 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-04-11 17:00:49 +0100
commit6670b494fdb23f74ecd9be3d952c007f64e268f1 (patch)
tree79b7373bbae600f3cc6992d171d99f6f2a870d6d /tcg/mips/tcg-target.inc.c
parent6523eaca378df1455481f1cec65ada589d65df0e (diff)
downloadqemu-arm-6670b494fdb23f74ecd9be3d952c007f64e268f1.tar.gz
hw/char/cmsdk-apb-uart.c: Correctly clear INTSTATUS bits on writes
The CMSDK APB UART INTSTATUS register bits are all write-one-to-clear. We were getting this correct for the TXO and RXO bits (which need special casing because their state lives in the STATE register), but had forgotten to handle the normal bits for RX and TX which we do store in our s->intstatus field. Perform the W1C operation on the bits in s->intstatus too. Fixes: https://bugs.launchpad.net/qemu/+bug/1760262 Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180410134203.17552-1-peter.maydell@linaro.org
Diffstat (limited to 'tcg/mips/tcg-target.inc.c')
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