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authorAurelien Jarno <aurelien@aurel32.net>2011-01-10 18:30:05 +0100
committerAurelien Jarno <aurelien@aurel32.net>2011-01-12 00:06:07 +0100
commit56779034530944eb6171d843f652f3fba710ed30 (patch)
treebdb4eb8143f70a010b216e2c9921f7bb84fac55b /tcg/arm
parentdace20dcc98f90a931e88aa641f5633cdcf30c30 (diff)
tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that people developping new targets based on existing ones are warned of the issue. Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/arm')
-rw-r--r--tcg/arm/tcg-target.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 1eb5605f8c..918e2f73cb 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -352,6 +352,9 @@ static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
{
+ /* We pay attention here to not modify the branch target by skipping
+ the corresponding bytes. This ensure that caches and memory are
+ kept coherent during retranslation. */
#ifdef HOST_WORDS_BIGENDIAN
tcg_out8(s, (cond << 4) | 0x0a);
s->code_ptr += 3;