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authorNikunj A Dadhania <nikunj@linux.vnet.ibm.com>2017-04-27 10:48:21 +0530
committerDavid Gibson <david@gibson.dropbear.id.au>2017-05-11 09:45:14 +1000
commit4771df23ed6a2b13927030d5933147d85785f5d5 (patch)
tree6065972f67b78f9df8cf5a7f3f4b2c7aec22b311 /target
parent7f9af1abdcc69fd1d3d8d2be68464329600616d6 (diff)
target/ppc: Generate fence operations
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
-rw-r--r--target/ppc/translate.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 50b6d4dcd8..4a1f24a54f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2971,6 +2971,7 @@ static void gen_stswx(DisasContext *ctx)
/* eieio */
static void gen_eieio(DisasContext *ctx)
{
+ tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
}
#if !defined(CONFIG_USER_ONLY)
@@ -3008,6 +3009,7 @@ static void gen_isync(DisasContext *ctx)
if (!ctx->pr) {
gen_check_tlb_flush(ctx, false);
}
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
gen_stop_exception(ctx);
}
@@ -3028,6 +3030,7 @@ static void gen_##name(DisasContext *ctx) \
tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
tcg_gen_mov_tl(cpu_reserve, t0); \
tcg_gen_mov_tl(cpu_reserve_val, gpr); \
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
tcg_temp_free(t0); \
}
@@ -3177,6 +3180,10 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
tcg_gen_br(l2);
gen_set_label(l1);
+
+ /* Address mismatch implies failure. But we still need to provide the
+ memory barrier semantics of the instruction. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
gen_set_label(l2);
@@ -3308,6 +3315,7 @@ static void gen_sync(DisasContext *ctx)
if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
gen_check_tlb_flush(ctx, true);
}
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
}
/* wait */