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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-08-13 19:48:49 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-10-17 11:13:15 +0200
commit4a367cfb00d3779f0113f871e4b7cb550d068098 (patch)
treeae8eb92623098aee659a682571c97cb62191bd95 /target
parent90e22a57af975dea08b3015dfac072709f131616 (diff)
downloadqemu-arm-4a367cfb00d3779f0113f871e4b7cb550d068098.tar.gz
target/mips/op_helper: Convert multiple if() to switch case
The cache operation is encoded in bits [20:18] of the instruction. The 'op' argument of helper_cache() contains the bits [20:16]. Extract the 3 bits and parse them using a switch case. This allow us to handle multiple cache types (the cache type is encoded in bits [17:16]). Previously the if() block was only checking the D-Cache (Primary Data or Unified Primary). Now we also handle the I-Cache (Primary Instruction), S-Cache (Secondary) and T-Cache (Terciary). Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-2-f4bug@amsat.org>
Diffstat (limited to 'target')
-rw-r--r--target/mips/op_helper.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 9552b280e0..c15f5c0776 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1574,15 +1574,20 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
#ifndef CONFIG_USER_ONLY
+ uint32_t cache_operation = extract32(op, 2, 3);
target_ulong index = addr & 0x1fffffff;
- if (op == 9) {
- /* Index Store Tag */
+
+ switch (cache_operation) {
+ case 0b010: /* Index Store Tag */
memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
- } else if (op == 5) {
- /* Index Load Tag */
+ break;
+ case 0b001: /* Index Load Tag */
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED);
+ break;
+ default:
+ break;
}
#endif
}