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authorAlistair Francis <alistair.francis@wdc.com>2020-12-16 10:22:26 -0800
committerAlistair Francis <alistair.francis@wdc.com>2020-12-17 21:56:43 -0800
commit617448a46b60c353fae0c645a024b628c1f9f700 (patch)
tree9a9ba6c916e9e59a6448f94c880902e373cb2f6d /target
parent54a581c22831098e53552d7e33024dc9f4193d7f (diff)
hw/riscv: Expand the is 32-bit check to support more CPUs
Currently the riscv_is_32_bit() function only supports the generic rv32 CPUs. Extend the function to support the SiFive and LowRISC CPUs as well. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
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