diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-09-03 14:32:07 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-14 14:23:19 +0100 |
| commit | 6cf0f240e0b980a877abed12d2995f740eae6515 (patch) | |
| tree | 19f1e9b9c36b9ab5a4bcfc6e96c073d4e376a2ea /target/arm/translate-neon.c.inc | |
| parent | acfdd2398dc929d4e87507b8acbdc19c88379e0e (diff) | |
target/arm: Convert Neon 3-same-fp size field to MO_* in decode
In the Neon instructions, some instruction formats have a 2-bit size
field which corresponds exactly to QEMU's MO_8/16/32/64. However the
floating-point insns in the 3-same group have a 1-bit size field
which is "0 for 32-bit float and 1 for 16-bit float". Currently we
pass these values directly through to trans_ functions, which means
that when reading a particular trans_ function you need to know if
that insn uses a 2-bit size or a 1-bit size.
Move the handling of the 1-bit size to the decodetree file, so that
all these insns consistently pass a size to the trans_ function which
is an MO_8/16/32/64 value.
In this commit we switch over the insns using the 3same_fp and
3same_fp_q0 formats.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-2-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate-neon.c.inc')
| -rw-r--r-- | target/arm/translate-neon.c.inc | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 2d4926316a..255c1cf8a2 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -49,6 +49,12 @@ static inline int rsub_8(DisasContext *s, int x) return 8 - x; } +static inline int neon_3same_fp_size(DisasContext *s, int x) +{ + /* Convert 0==fp32, 1==fp16 into a MO_* value */ + return MO_32 - x; +} + /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" @@ -1049,7 +1055,7 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) WRAP_FP_GVEC(gen_##INSN##_fp16_3s, FPST_STD_F16, HFUNC) \ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ { \ - if (a->size != 0) { \ + if (a->size == MO_16) { \ if (!dc_isar_feature(aa32_fp16_arith, s)) { \ return false; \ } \ @@ -1088,7 +1094,7 @@ static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a) return false; } - if (a->size != 0) { + if (a->size == MO_16) { if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -1103,7 +1109,7 @@ static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a) return false; } - if (a->size != 0) { + if (a->size == MO_16) { if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -1135,7 +1141,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, assert(a->q == 0); /* enforced by decode patterns */ - fpstatus = fpstatus_ptr(a->size != 0 ? FPST_STD_F16 : FPST_STD); + fpstatus = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), @@ -1152,7 +1158,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, #define DO_3S_FP_PAIR(INSN,FUNC) \ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ { \ - if (a->size != 0) { \ + if (a->size == MO_16) { \ if (!dc_isar_feature(aa32_fp16_arith, s)) { \ return false; \ } \ |