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authorPeter Maydell <peter.maydell@linaro.org>2021-06-17 13:16:28 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-06-21 17:12:52 +0100
commitd93a468d1302f29afcb1e368fb39da3fe024fc39 (patch)
tree8fc675bf353a29557f5298ceff549866c2b6f24c /target/arm/translate-a32.h
parent3e6d6e88d915d0fea1fbbf530801e2aec9df2d0d (diff)
downloadqemu-arm-d93a468d1302f29afcb1e368fb39da3fe024fc39.tar.gz
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
In a CPU with MVE, the VMOV (vector lane to general-purpose register) and VMOV (general-purpose register to vector lane) insns are not predicated, but they are subject to beatwise execution if they are not in an IT block. Since our implementation always executes all 4 beats in one tick, this means only that we need to handle PSR.ECI: * we must do the usual check for bad ECI state * we must advance ECI state if the insn succeeds * if ECI says we should not be executing the beat corresponding to the lane of the vector register being accessed then we should skip performing the move Note that if PSR.ECI is non-zero then we cannot be in an IT block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-45-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate-a32.h')
-rw-r--r--target/arm/translate-a32.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index 2326405300..6dfcafe179 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -47,6 +47,8 @@ long neon_full_reg_offset(unsigned reg);
long neon_element_offset(int reg, int element, MemOp memop);
void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
void clear_eci_state(DisasContext *s);
+bool mve_eci_check(DisasContext *s);
+void mve_update_and_store_eci(DisasContext *s);
static inline TCGv_i32 load_cpu_offset(int offset)
{