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authorPeter Maydell <peter.maydell@linaro.org>2021-06-28 14:58:35 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-07-02 11:48:38 +0100
commit04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8 (patch)
tree96c7bb61af69450637772d4ff5c8dd67afabfe94 /target/arm/t32.decode
parent46321d47a91499897bd032361dc24013d70f21a5 (diff)
downloadqemu-arm-04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8.tar.gz
target/arm: Implement MVE shifts by registerpull-target-arm-20210702
Implement the MVE shifts by register, which perform shifts on a single general-purpose register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/t32.decode')
-rw-r--r--target/arm/t32.decode18
1 files changed, 14 insertions, 4 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 1c3406c67a..2d47f31f14 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -51,6 +51,7 @@
&mve_shl_ri rdalo rdahi shim
&mve_shl_rr rdalo rdahi rm
&mve_sh_ri rda shim
+&mve_sh_rr rda rm
# rdahi: bits [3:1] from insn, bit 0 is 1
# rdalo: bits [3:1] from insn, bit 0 is 0
@@ -74,6 +75,7 @@
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
&mve_sh_ri shim=%imm5_12_6
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
{
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
@@ -112,10 +114,18 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
}
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
+ {
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
+ }
+
+ {
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
+ }
+
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
]