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authorPeter Maydell <peter.maydell@linaro.org>2017-02-20 14:04:41 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-20 14:04:41 +0000
commit6cbf97bf937743974938464d11f5dcd0366d0709 (patch)
tree2cec3986628a27a8f39962a00334be0fc84a1e19 /target/arm/cpu.h
parentb6a915dec8706e427f75231c8fc1ee728a1cef02 (diff)
downloadqemu-arm-6cbf97bf937743974938464d11f5dcd0366d0709.tar.gz
armv7m: Fix condition check for taking exceptions
The M profile condition for when we can take a pending exception or interrupt is not the same as that for A/R profile. The code originally copied from the A/R profile version of the cpu_exec_interrupt function only worked by chance for the very simple case of exceptions being masked by PRIMASK. Replace it with a call to a function in the NVIC code that correctly compares the priority of the pending exception against the current execution priority of the CPU. [Michael Davidsaver's patchset had a patch to do something similar but the implementation ended up being a rewrite.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0956a54e89..53299fa2c1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1342,6 +1342,14 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure);
/* Interface between CPU and Interrupt controller. */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_can_take_pending_exception(void *opaque);
+#else
+static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+{
+ return true;
+}
+#endif
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);