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authorPeter Maydell <peter.maydell@linaro.org>2017-02-28 12:08:19 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-28 12:08:19 +0000
commitaa488fe3bb5460c6675800ccd80f6dccbbd70159 (patch)
tree7bdaadadae7c270049e14f8fdca1a1abcdfba756 /target/arm/cpu.h
parent39ae2474e337247e5930e8be783b689adc9f6215 (diff)
downloadqemu-arm-aa488fe3bb5460c6675800ccd80f6dccbbd70159.tar.gz
armv7m: Check exception return consistency
Implement the exception return consistency checks described in the v7M pseudocode ExceptionReturn(). Inspired by a patch from Michael Davidsaver's series, but this is a reimplementation from scratch based on the ARM ARM pseudocode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 68ad00c480..045830aeae 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1366,7 +1366,17 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
#endif
void armv7m_nvic_set_pending(void *opaque, int irq);
void armv7m_nvic_acknowledge_irq(void *opaque);
-void armv7m_nvic_complete_irq(void *opaque, int irq);
+/**
+ * armv7m_nvic_complete_irq: complete specified interrupt or exception
+ * @opaque: the NVIC
+ * @irq: the exception number to complete
+ *
+ * Returns: -1 if the irq was not active
+ * 1 if completing this irq brought us back to base (no active irqs)
+ * 0 if there is still an irq active after this one was completed
+ * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
+ */
+int armv7m_nvic_complete_irq(void *opaque, int irq);
/* Interface for defining coprocessor registers.
* Registers are defined in tables of arm_cp_reginfo structs