aboutsummaryrefslogtreecommitdiff
path: root/target-xtensa
diff options
context:
space:
mode:
authorMax Filippov <jcmvbkbc@gmail.com>2011-09-06 03:55:39 +0400
committerBlue Swirl <blauwirbel@gmail.com>2011-09-10 16:57:38 +0000
commit8ffc2d0d97a59b25b48d023838906d5850e73184 (patch)
tree8ee8749695c8a94917e3c376a06ccf7d7db2638e /target-xtensa
parent28067b2288c70d7ce9a3735a777b73a627c71a1f (diff)
target-xtensa: implement CACHE group
All operations in this group are no-ops, because cache ought to be transparent to applications. However cache may be abused, then we'll need to actually implement these opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa')
-rw-r--r--target-xtensa/translate.c95
1 files changed, 94 insertions, 1 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 4f1c18eddb..7d383b3482 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1012,7 +1012,100 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 7: /*CACHEc*/
- TBD();
+ if (RRI8_T < 8) {
+ HAS_OPTION(XTENSA_OPTION_DCACHE);
+ }
+
+ switch (RRI8_T) {
+ case 0: /*DPFRc*/
+ break;
+
+ case 1: /*DPFWc*/
+ break;
+
+ case 2: /*DPFROc*/
+ break;
+
+ case 3: /*DPFWOc*/
+ break;
+
+ case 4: /*DHWBc*/
+ break;
+
+ case 5: /*DHWBIc*/
+ break;
+
+ case 6: /*DHIc*/
+ break;
+
+ case 7: /*DIIc*/
+ break;
+
+ case 8: /*DCEc*/
+ switch (OP1) {
+ case 0: /*DPFLl*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ break;
+
+ case 2: /*DHUl*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ break;
+
+ case 3: /*DIUl*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
+ break;
+
+ case 4: /*DIWBc*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE);
+ break;
+
+ case 5: /*DIWBIc*/
+ HAS_OPTION(XTENSA_OPTION_DCACHE);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+
+ }
+ break;
+
+ case 12: /*IPFc*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE);
+ break;
+
+ case 13: /*ICEc*/
+ switch (OP1) {
+ case 0: /*IPFLl*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ break;
+
+ case 2: /*IHUl*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ break;
+
+ case 3: /*IIUl*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
+ break;
+
+ case 14: /*IHIc*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE);
+ break;
+
+ case 15: /*IIIc*/
+ HAS_OPTION(XTENSA_OPTION_ICACHE);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
break;
case 9: /*L16SI*/