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authorMax Filippov <jcmvbkbc@gmail.com>2011-09-06 03:55:35 +0400
committerBlue Swirl <blauwirbel@gmail.com>2011-09-10 16:57:38 +0000
commit3580ecad0acf25a28464c145f2c74a929d0e57b1 (patch)
treea608720eeb1e6e6dfb289682b91781d803bcad20 /target-xtensa/op_helper.c
parentb8132eff891bce658b799df20748a1cb39f4dc06 (diff)
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA(U); - RST1: shifts, 16-bit multiplication. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/op_helper.c')
-rw-r--r--target-xtensa/op_helper.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 0392fbe6bb..c1cfd2ea7b 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -28,6 +28,7 @@
#include "cpu.h"
#include "dyngen-exec.h"
#include "helpers.h"
+#include "host-utils.h"
#define MMUSUFFIX _mmu
@@ -57,3 +58,16 @@ void HELPER(exception)(uint32_t excp)
env->exception_index = excp;
cpu_loop_exit(env);
}
+
+uint32_t HELPER(nsa)(uint32_t v)
+{
+ if (v & 0x80000000) {
+ v = ~v;
+ }
+ return v ? clz32(v) - 1 : 31;
+}
+
+uint32_t HELPER(nsau)(uint32_t v)
+{
+ return v ? clz32(v) : 32;
+}