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authorMax Filippov <jcmvbkbc@gmail.com>2012-05-27 18:34:52 +0400
committerBlue Swirl <blauwirbel@gmail.com>2012-06-09 10:45:03 +0000
commitae4e7982e6db8b88e90db74779f4693bc2c636a8 (patch)
tree648a6211b3d7923e9e66cc058753491ccf54e6a9 /target-xtensa/cpu.h
parent16bde77a298acfe15f5e948aceff550d0cb173e8 (diff)
target-xtensa: update autorefill TLB entries conditionally
This is to avoid interference of internal QEMU helpers (cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visible TLB state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
-rw-r--r--target-xtensa/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index c2ca509698..f7db116400 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -386,7 +386,7 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
-int xtensa_get_physical_addr(CPUXtensaState *env,
+int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access);
void reset_mmu(CPUXtensaState *env);