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authorMax Filippov <jcmvbkbc@gmail.com>2011-09-06 03:55:35 +0400
committerBlue Swirl <blauwirbel@gmail.com>2011-09-10 16:57:38 +0000
commit3580ecad0acf25a28464c145f2c74a929d0e57b1 (patch)
treea608720eeb1e6e6dfb289682b91781d803bcad20 /target-xtensa/cpu.h
parentb8132eff891bce658b799df20748a1cb39f4dc06 (diff)
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA(U); - RST1: shifts, 16-bit multiplication. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
-rw-r--r--target-xtensa/cpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 8c3fe2e1ba..f756b430aa 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -105,6 +105,10 @@ enum {
FSR = 233,
};
+enum {
+ SAR = 3,
+};
+
typedef struct XtensaConfig {
const char *name;
uint64_t options;