diff options
| author | Andreas Färber <afaerber@suse.de> | 2013-06-21 22:29:57 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-09 21:33:04 +0200 |
| commit | 62a80559368de7b2dedc91039d8d11650e31ba4c (patch) | |
| tree | 83f992013c599765aafc99879e1de4c8c57334de /target-unicore32 | |
| parent | 68a471556d911a0adcf639e5fd5af2a2be4c4cb1 (diff) | |
target-unicore32: Change gen_intermediate_code_internal() signature
Use UniCore32CPU and bool.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-unicore32')
| -rw-r--r-- | target-unicore32/translate.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index e1fe4e6bca..d85185df36 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1876,9 +1876,10 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline void gen_intermediate_code_internal(CPUUniCore32State *env, - TranslationBlock *tb, int search_pc) +static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, + TranslationBlock *tb, bool search_pc) { + CPUUniCore32State *env = &cpu->env; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; uint16_t *gen_opc_end; @@ -2065,12 +2066,12 @@ done_generating: void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 0); + gen_intermediate_code_internal(uc32_env_get_cpu(env), tb, false); } void gen_intermediate_code_pc(CPUUniCore32State *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 1); + gen_intermediate_code_internal(uc32_env_get_cpu(env), tb, true); } static const char *cpu_mode_names[16] = { |