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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-05-11 14:59:55 +0200
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-05-22 17:02:34 +0200
commit9371557115a734412974f8d4096cbe8a62ca2731 (patch)
tree7aedb471780d228438883c34b08fdc13084de5ea /target-tricore/translate.c
parent0e045f43c45f675711c3f6836118dc7eabcc2411 (diff)
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/translate.c')
-rw-r--r--target-tricore/translate.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index d4e4226f69..5f8eff04fa 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -201,6 +201,15 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
tcg_temp_free_i64(arg1); \
} while (0)
+#define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
+ TCGv_i64 ret = tcg_temp_new_i64(); \
+ \
+ gen_helper_##name(ret, cpu_env, arg1, arg2); \
+ tcg_gen_extr_i64_i32(rl, rh, ret); \
+ \
+ tcg_temp_free_i64(ret); \
+} while (0)
+
#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
((offset & 0x0fffff) << 1))
@@ -6494,6 +6503,18 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
} /* TODO: else raise illegal opcode trap */
break;
+ case OPC2_32_RR_DIV:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+ cpu_gpr_d[r2]);
+ } /* TODO: else raise illegal opcode trap */
+ break;
+ case OPC2_32_RR_DIV_U:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
+ cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ } /* TODO: else raise illegal opcode trap */
+ break;
}
}