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authorRichard Henderson <rth@twiddle.net>2015-08-22 10:42:44 -0700
committerRichard Henderson <rth@twiddle.net>2015-09-15 07:45:33 -0700
commit661ff7431fb33bc29c6b27e053e1e7656105a106 (patch)
tree071b0bff84a08e7b2d95f5a36ab3d495a2165892 /target-tilegx
parent4ff49775ecc5e975ca5e4c1b6be25fb611ab38fa (diff)
downloadqemu-arm-661ff7431fb33bc29c6b27e053e1e7656105a106.tar.gz
target-tilegx: Handle mask instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx')
-rw-r--r--target-tilegx/translate.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 673b4418da..8b7c7199ce 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -643,11 +643,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(FSINGLE_MUL2, 0, X0):
case OE_RRR(FSINGLE_PACK2, 0, X0):
case OE_RRR(FSINGLE_SUB1, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(MNZ, 0, X0):
case OE_RRR(MNZ, 0, X1):
case OE_RRR(MNZ, 4, Y0):
case OE_RRR(MNZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mnz";
+ break;
case OE_RRR(MULAX, 0, X0):
case OE_RRR(MULAX, 3, Y0):
tcg_gen_mul_tl(tdest, tsrca, tsrcb);
@@ -763,7 +767,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(MZ, 0, X1):
case OE_RRR(MZ, 4, Y0):
case OE_RRR(MZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mz";
+ break;
case OE_RRR(NOR, 0, X0):
case OE_RRR(NOR, 0, X1):
case OE_RRR(NOR, 5, Y0):