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authorRichard Henderson <rth@twiddle.net>2015-08-24 08:13:59 -0700
committerRichard Henderson <rth@twiddle.net>2015-09-15 07:45:34 -0700
commit3be19e8c83949b62895dd27866e26a1bf806ad56 (patch)
tree62c2a80091a0a3484a4d8971ba78659d9de11278 /target-tilegx
parent5151c69abcc049a587b894f0b8e19e1c6d72dc1d (diff)
downloadqemu-arm-3be19e8c83949b62895dd27866e26a1bf806ad56.tar.gz
target-tilegx: Handle v1shli, v1shrui
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx')
-rw-r--r--target-tilegx/translate.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 7719132f89..65b610e542 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1198,6 +1198,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
TCGv tsrca = load_gr(dc, srca);
const char *mnemonic;
TCGMemOp memop;
+ int i2, i3;
switch (opext) {
case OE(ADDI_OPCODE_Y0, 0, Y0):
@@ -1392,10 +1393,23 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
break;
case OE_SH(V1SHLI, X0):
case OE_SH(V1SHLI, X1):
+ i2 = imm & 7;
+ i3 = 0xff >> i2;
+ tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
+ tcg_gen_shli_tl(tdest, tdest, i2);
+ mnemonic = "v1shli";
+ break;
case OE_SH(V1SHRSI, X0):
case OE_SH(V1SHRSI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_SH(V1SHRUI, X0):
case OE_SH(V1SHRUI, X1):
+ i2 = imm & 7;
+ i3 = (0xff << i2) & 0xff;
+ tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
+ tcg_gen_shri_tl(tdest, tdest, i2);
+ mnemonic = "v1shrui";
+ break;
case OE_SH(V2SHLI, X0):
case OE_SH(V2SHLI, X1):
case OE_SH(V2SHRSI, X0):