aboutsummaryrefslogtreecommitdiff
path: root/target-tilegx
diff options
context:
space:
mode:
authorChen Gang <gang.chen.5i5j@gmail.com>2015-09-22 05:47:35 +0800
committerRichard Henderson <rth@twiddle.net>2015-10-07 20:03:13 +1100
commit0ab0a3d768a4f6ab6747b6fd936c5cf70b5069c2 (patch)
tree10d80bde7b4cc69fda80462a5318bcade3549651 /target-tilegx
parent055130107683c3b199c1848a25e5e2c568230cbf (diff)
downloadqemu-arm-0ab0a3d768a4f6ab6747b6fd936c5cf70b5069c2.tar.gz
target-tilegx: Implement v*shl, v*shru, and v*shrs instructions
v2sh* are implemented with helper functions; v4sh* are implmeneted with inline code. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx')
-rw-r--r--target-tilegx/helper.h3
-rw-r--r--target-tilegx/simd_helper.c31
-rw-r--r--target-tilegx/translate.c39
3 files changed, 73 insertions, 0 deletions
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 766f5f2f9c..b253722a72 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -8,3 +8,6 @@ DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index f573f9b51a..1c59a92216 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -25,6 +25,7 @@
/* Broadcast a value to all elements of a vector. */
#define V1(X) (((X) & 0xff) * 0x0101010101010101ull)
+#define V2(X) (((X) & 0xffff) * 0x0001000100010001ull)
uint64_t helper_v1shl(uint64_t a, uint64_t b)
@@ -36,6 +37,15 @@ uint64_t helper_v1shl(uint64_t a, uint64_t b)
return (a & m) << b;
}
+uint64_t helper_v2shl(uint64_t a, uint64_t b)
+{
+ uint64_t m;
+
+ b &= 15;
+ m = V2(0xffff >> b);
+ return (a & m) << b;
+}
+
uint64_t helper_v1shru(uint64_t a, uint64_t b)
{
uint64_t m;
@@ -45,6 +55,15 @@ uint64_t helper_v1shru(uint64_t a, uint64_t b)
return (a & m) >> b;
}
+uint64_t helper_v2shru(uint64_t a, uint64_t b)
+{
+ uint64_t m;
+
+ b &= 15;
+ m = V2(0xffff << b);
+ return (a & m) >> b;
+}
+
uint64_t helper_v1shrs(uint64_t a, uint64_t b)
{
uint64_t r = 0;
@@ -56,3 +75,15 @@ uint64_t helper_v1shrs(uint64_t a, uint64_t b)
}
return r;
}
+
+uint64_t helper_v2shrs(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ b &= 15;
+ for (i = 0; i < 64; i += 16) {
+ r = deposit64(r, i, 16, sextract64(a, i + b, 16 - b));
+ }
+ return r;
+}
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index e70c3e5ab7..92287510f3 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -339,6 +339,25 @@ static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb
return TILEGX_EXCP_NONE;
}
+static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
+ void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 al = tcg_temp_new_i32();
+ TCGv_i32 ah = tcg_temp_new_i32();
+ TCGv_i32 bl = tcg_temp_new_i32();
+
+ tcg_gen_extr_i64_i32(al, ah, a64);
+ tcg_gen_extrl_i64_i32(bl, b64);
+ tcg_gen_andi_i32(bl, bl, 31);
+ generate(al, al, bl);
+ generate(ah, ah, bl);
+ tcg_gen_concat_i32_i64(d64, al, ah);
+
+ tcg_temp_free_i32(al);
+ tcg_temp_free_i32(ah);
+ tcg_temp_free_i32(bl);
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -1144,12 +1163,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V2SADU, 0, X0):
case OE_RRR(V2SHLSC, 0, X0):
case OE_RRR(V2SHLSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2SHL, 0, X0):
case OE_RRR(V2SHL, 0, X1):
+ gen_helper_v2shl(tdest, tsrca, tsrcb);
+ mnemonic = "v2shl";
+ break;
case OE_RRR(V2SHRS, 0, X0):
case OE_RRR(V2SHRS, 0, X1):
+ gen_helper_v2shrs(tdest, tsrca, tsrcb);
+ mnemonic = "v2shrs";
+ break;
case OE_RRR(V2SHRU, 0, X0):
case OE_RRR(V2SHRU, 0, X1):
+ gen_helper_v2shru(tdest, tsrca, tsrcb);
+ mnemonic = "v2shru";
+ break;
case OE_RRR(V2SUBSC, 0, X0):
case OE_RRR(V2SUBSC, 0, X1):
case OE_RRR(V2SUB, 0, X0):
@@ -1174,12 +1203,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V4PACKSC, 0, X1):
case OE_RRR(V4SHLSC, 0, X0):
case OE_RRR(V4SHLSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4SHL, 0, X0):
case OE_RRR(V4SHL, 0, X1):
+ gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32);
+ mnemonic = "v4shl";
+ break;
case OE_RRR(V4SHRS, 0, X0):
case OE_RRR(V4SHRS, 0, X1):
+ gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32);
+ mnemonic = "v4shrs";
+ break;
case OE_RRR(V4SHRU, 0, X0):
case OE_RRR(V4SHRU, 0, X1):
+ gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32);
+ mnemonic = "v4shru";
+ break;
case OE_RRR(V4SUBSC, 0, X0):
case OE_RRR(V4SUBSC, 0, X1):
case OE_RRR(V4SUB, 0, X0):