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authorChen Gang <gang.chen.5i5j@gmail.com>2015-10-04 17:41:14 +0800
committerRichard Henderson <rth@twiddle.net>2015-10-07 20:24:04 +1100
commitfec7daab3d63b7b2ca61581fffc40142b22b2bd5 (patch)
tree265ec0eb27679df78f101410447fb1376627a405 /target-tilegx/cpu.h
parent77b3adc0012153e629b48b710ad19a8b544bb507 (diff)
downloadqemu-arm-fec7daab3d63b7b2ca61581fffc40142b22b2bd5.tar.gz
target-tilegx: Support iret instruction and related special registers
EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or it will cause target SIGILL (and the patch doesn't support system mode). Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx/cpu.h')
-rw-r--r--target-tilegx/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 6f04fe7fb2..6c0fd5365d 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -53,6 +53,8 @@ enum {
TILEGX_SPR_CMPEXCH = 0,
TILEGX_SPR_CRITICAL_SEC = 1,
TILEGX_SPR_SIM_CONTROL = 2,
+ TILEGX_SPR_EX_CONTEXT_0_0 = 3,
+ TILEGX_SPR_EX_CONTEXT_0_1 = 4,
TILEGX_SPR_COUNT
};