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authorTsuneo Saito <tsnsaito@gmail.com>2011-07-23 11:20:06 +0900
committerBlue Swirl <blauwirbel@gmail.com>2011-07-30 08:26:45 +0000
commitccb57e0ea74892a29969f9a28c67df3fdcb5259d (patch)
treef2b5d41461e3eb2dbb38a90e1ba26e53c2e43cd7 /target-sparc/translate.c
parent5e37141bbb9796ef139aee902a882ca97d59b84d (diff)
SPARC64: fix fnor* and fnand*
Fix the problem that result values are not assigned to the destination registers. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/translate.c')
-rw-r--r--target-sparc/translate.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 15967c551a..f68b3bcdd8 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3980,14 +3980,15 @@ static void disas_sparc_insn(DisasContext * dc)
break;
case 0x062: /* VIS I fnor */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ tcg_gen_nor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
cpu_fpr[DFPREG(rs2)]);
- tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ tcg_gen_nor_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x063: /* VIS I fnors */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ tcg_gen_nor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x064: /* VIS I fandnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -4047,14 +4048,15 @@ static void disas_sparc_insn(DisasContext * dc)
break;
case 0x06e: /* VIS I fnand */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ tcg_gen_nand_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
cpu_fpr[DFPREG(rs2)]);
- tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ tcg_gen_nand_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x06f: /* VIS I fnands */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ tcg_gen_nand_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x070: /* VIS I fand */
CHECK_FPU_FEATURE(dc, VIS1);