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authorAurelien Jarno <aurelien@aurel32.net>2015-05-25 01:28:56 +0200
committerAurelien Jarno <aurelien@aurel32.net>2015-06-12 12:02:48 +0200
commitd0f44a55fa321e042bd6b2a0fa25ac48864b7a25 (patch)
tree92fa37119083a4792f1e96a54886fa1364164ca2 /target-sh4/translate.c
parenta2368e01c95a093d250a0e5d3cef53dddf642f1e (diff)
downloadqemu-arm-d0f44a55fa321e042bd6b2a0fa25ac48864b7a25.tar.gz
target-sh4: optimize subc using sub2
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/translate.c')
-rw-r--r--target-sh4/translate.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 5c90fe3f31..b8abfd5052 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -880,19 +880,15 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x300a: /* subc Rm,Rn */
{
- TCGv t0, t1, t2;
- t0 = tcg_temp_new();
+ TCGv t0, t1;
+ t0 = tcg_const_tl(0);
t1 = tcg_temp_new();
- tcg_gen_sub_i32(t1, REG(B11_8), REG(B7_4));
- tcg_gen_sub_i32(t0, t1, cpu_sr_t);
- t2 = tcg_temp_new();
- tcg_gen_setcond_i32(TCG_COND_LTU, t2, REG(B11_8), t1);
- tcg_gen_setcond_i32(TCG_COND_LTU, t1, t1, t0);
- tcg_gen_or_i32(cpu_sr_t, t1, t2);
- tcg_temp_free(t2);
- tcg_temp_free(t1);
- tcg_gen_mov_i32(REG(B11_8), t0);
+ tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
+ tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
+ REG(B11_8), t0, t1, cpu_sr_t);
+ tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
tcg_temp_free(t0);
+ tcg_temp_free(t1);
}
return;
case 0x300b: /* subv Rm,Rn */